Datasheet

Table 1. Revision History (continued)
DescriptionRevisionDate
■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ
to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register.
■ Added "Reset Sources" table to System Control chapter.
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be four-bits
wide, bits[7:4].
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added note that specific module clocks must be enabled before that module's registers can be
programmed. There must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.
■ Changed I
2
C slave register base addresses and offsets to be relative to the I
2
C module base address
of 0x4002.0000 , so register bases and offsets were changed for all I
2
C slave registers. Note that
the hw_i2c.h file in the StellarisWare
®
Driver Library uses a base address of 0x4002.0800 for the
I
2
C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that
StellarisWare uses the old slave base address for these offsets.
■ Added GNDPHY and VCCPHY to Connections for Unused Signals tables.
■ Corrected nonlinearity and offset error parameters (E
L
, E
D
and E
O
) in ADC Characteristics table.
■ Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (V
NON
parameter in Maximum Ratings table).
■ Additional minor data sheet clarifications and corrections.
9102January 2011
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
■ Changed register names to be consistent with StellarisWare names: the Cortex-M3 Interrupt Control
and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the
Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register.
■ Added clarification of instruction execution during Flash operations.
■ Modified Figure 8-1 on page 295 to clarify operation of the GPIO inputs when used as an alternate
function.
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits
wide, bits[7:0].
■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In Electrical Characteristics chapter:
– Added I
LKG
parameter (GPIO input leakage current) to Table 23-4 on page 749.
– Corrected values for t
CLKRF
parameter (SSIClk rise/fall time) in Table 23-21 on page 759.
– Added "Ethernet Controller DC Characteristics" table (see Table 23-8 on page 751).
■ Added dimensions for Tray and Tape and Reel shipping mediums.
7787September 2010
June 18, 201228
Texas Instruments-Production Data
Revision History
NRND: Not recommended for new designs.