Datasheet

Note: Offset is relative to System Control base address of 0x400F.E000

This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.

The internal flash has specific minimum and maximum requirements on the length of time the high

voltage write pulse can be applied. It is required that this register contain the operating frequency

(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this

value if the clocking conditions are changed for a flash erase/program operation.

USec Reload (USECRL)

Base 0x400F.E000

Offset 0x140

Type R/W, reset 0x31

16171819202122232425262728293031

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

0123456789101112131415

USECreserved

R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType

1000110000000000Reset

DescriptionResetTypeNameBit/Field

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0x0ROreserved31:8

Microsecond Reload Value

MHz -1 of the controller clock when the flash is being erased or

programmed.

If the maximum system frequency is being used, USEC should be set to

0x31 (50 MHz) whenever the flash is being erased or programmed.

0x31R/WUSEC7:0

277June 18, 2012

Texas Instruments-Production Data

Stellaris

LM3S8962 Microcontroller

NRND: Not recommended for new designs.