Datasheet

Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AMISCPMISCreserved
R/W1CR/W1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:2
Programming Masked Interrupt Status and Clear
DescriptionValue
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 273).
1
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
0R/W1CPMISC1
Access Masked Interrupt Status and Clear
DescriptionValue
When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 273).
1
When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.
0
0R/W1CAMISC0
275June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.