Datasheet

Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCALT0RTCALT1LOWBATEXTWreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000.0000ROreserved31:4
External Wake-Up Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WEXTW3
Low Battery Voltage Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WLOWBAT2
RTC Alert1 Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WRTCALT11
RTC Alert0 Interrupt Mask
DescriptionValue
Masked0
Unmasked1
0R/WRTCALT00
257June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.