Datasheet

Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x8000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RTCENHIBREQCLKSELRTCWENPINWEN
LOWBATEN
CLK32ENVABORTreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Power Cut Abort Enable
DescriptionValue
Power cut occurs during a low-battery alert.0
Power cut is aborted.1
0R/WVABORT7
Clocking Enable
DescriptionValue
Disabled0
Enabled1
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
0R/WCLK32EN6
Low Battery Monitoring Enable
DescriptionValue
Disabled0
Enabled1
When set, low battery voltage detection is enabled (V
BAT
< V
LOWBAT
).
0R/WLOWBATEN5
External WAKE Pin Enable
DescriptionValue
Disabled0
Enabled1
When set, an external event on the WAKE pin will re-power the device.
0R/WPINWEN4
255June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.