Datasheet

Table 6-2. Hibernate Signals (108BGA)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODOM12HIB
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
Power-L12VBAT
An external input that brings the processor out of Hibernate
mode when asserted.
TTLIM10WAKE
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
AnalogIK11XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
AnalogOK12XOSC1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
6.3 Functional Description
The Hibernation module controls the power to the processor with an enable signal (HIB) that signals
an external voltage regulator to turn off.
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (V
DD
) or the battery/auxilliary voltage
source (V
BAT
). A voting circuit indicates the larger and an internal power switch selects the appropriate
voltage source. The Hibernation module also has a separate clock source to maintain a real-time
clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on
the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain
value. The Hibernation module can also detect when the battery voltage is low, and optionally
prevent hibernation when this occurs.
When waking from hibernation, the HIB signal is deasserted. The return of V
DD
causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (t
WAKE_TO_HIB
) plus the power-on reset time (T
IRPOR
).
6.3.1 Register Access Timing
Because the Hibernation module has an independent clocking domain, certain registers must be
written only with a timing gap between accesses. The delay time is t
HIB_REG_WRITE
, therefore software
must guarantee that a delay of t
HIB_REG_WRITE
is inserted between back-to-back writes to certain
Hibernation registers, or between a write followed by a read to those same registers. There is no
restriction on timing for back-to-back reads from the Hibernation module. The following registers
are subject to this timing restriction:
■ Hibernation RTC Counter (HIBRTCC)
■ Hibernation RTC Match 0 (HIBRTCM0)
■ Hibernation RTC Match 1 (HIBRTCM1)
■ Hibernation RTC Load (HIBRTCLD)
■ Hibernation RTC Trim (HIBRTCT)
■ Hibernation Data (HIBDATA)
June 18, 2012244
Texas Instruments-Production Data
Hibernation Module
NRND: Not recommended for new designs.