Datasheet

6.1 Block Diagram
Figure 6-1. Hibernation Module Block Diagram
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
Pre-Divider
/128
XOSC0
XOSC1
HIBCTL.CLK32EN
HIBCTL.CLKSEL
HIBRTCC
HIBRTCLD
HIBRTCM0
HIBRTCM1
RTC
Interrupts
Power
Sequence
Logic
MATCH0/1
WAKE
Interrupts
to CPU
Low Battery
Detect
LOWBAT
V
DD
V
BAT
HIB
HIBCTL.LOWBATEN
HIBCTL.PWRCUT
HIBCTL.EXTWEN
HIBCTL.RTCWEN
HIBCTL.VABORT
Non-Volatile
Memory
64 words
HIBDATA
32.768 kHz
4.194304 MHz
6.2 Signal Description
Table 6-1 on page 243 and Table 6-2 on page 244 list the external signals of the Hibernation module
and describe the function of each. These signals have dedicated functions and are not alternate
functions for any GPIO signals.
Table 6-1. Hibernate Signals (100LQFP)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
ODO51HIB
Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
Power-55VBAT
An external input that brings the processor out of Hibernate
mode when asserted.
TTLI50WAKE
Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a
32.768-kHz oscillator for the Hibernation module RTC.
AnalogI52XOSC0
Hibernation module oscillator crystal output. Leave
unconnected when using a single-ended clock source.
AnalogO53XOSC1
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
243June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.