Datasheet

Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 531
Register 3: I
2
C Master Data (I2CMDR), offset 0x008 ......................................................................... 535
Register 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 536
Register 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 537
Register 6: I
2
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 538
Register 7: I
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 539
Register 8: I
2
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 540
Register 9: I
2
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 541
Register 10: I
2
C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 543
Register 11: I
2
C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 544
Register 12: I
2
C Slave Data (I2CSDR), offset 0x808 ........................................................................... 546
Register 13: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 547
Register 14: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 548
Register 15: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 549
Register 16: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 550
Controller Area Network (CAN) Module ..................................................................................... 551
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 573
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 575
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 577
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 578
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 579
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 580
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 582
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 583
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 583
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 584
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 584
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 586
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 586
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 587
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 587
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 588
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 588
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 589
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 589
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 591
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 591
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 593
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 593
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 593
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 593
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 593
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 593
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 593
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 593
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 594
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 594
23June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.