Datasheet

Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 445
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 447
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 449
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 450
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 451
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 452
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 454
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 456
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 458
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 460
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 461
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 462
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 464
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 465
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 466
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 467
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 468
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 469
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 470
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 471
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 472
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 473
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 474
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 475
Synchronous Serial Interface (SSI) ............................................................................................ 476
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 489
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 491
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 493
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 494
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 496
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 497
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 499
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 500
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 501
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 502
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 503
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 504
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 505
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 506
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 507
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 508
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 509
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 510
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 511
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 512
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 513
Inter-Integrated Circuit (I
2
C) Interface ........................................................................................ 514
Register 1: I
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 530
June 18, 201222
Texas Instruments-Production Data
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NRND: Not recommended for new designs.