Datasheet

Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 379
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 380
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 381
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 382
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 383
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 384
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 385
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 386
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 387
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 388
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 389
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 390
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 391
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 392
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 393
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 394
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 395
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 396
Analog-to-Digital Converter (ADC) ............................................................................................. 397
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 407
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 408
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 409
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 410
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 411
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 412
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 416
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 417
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 419
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 420
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 421
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 423
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 426
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 426
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 426
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 426
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 427
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 427
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 427
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 427
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 428
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 428
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 429
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 429
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 431
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 432
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 433
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 434
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 443
21June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.