Datasheet

Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0111.32FF
16171819202122232425262728293031
ADCreservedPWMreservedCAN0reserved
ROROROROROROROROROROROROROROROROType
1000100010000000Reset
0123456789101112131415
JTAGSWDSWOWDTPLLTEMPSNSHIBMPUMAXADCSPDreservedMINSYSDIV
ROROROROROROROROROROROROROROROROType
1111111101001100Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:25
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
1ROCAN024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:21
PWM Module Present
When set, indicates that the PWM module is present.
1ROPWM20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:17
ADC Module Present
When set, indicates that the ADC module is present.
1ROADC16
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
DescriptionValue
Specifies a 50-MHz CPU clock with a PLL divider of 4.0x3
0x3ROMINSYSDIV15:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:10
209June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.