Datasheet

Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 308
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 309
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 310
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 311
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 313
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 314
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 315
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 316
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 317
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 318
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 319
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 320
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 321
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 322
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 324
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 325
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 326
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 327
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 328
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 329
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 330
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 331
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 332
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 333
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 334
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 335
General-Purpose Timers ............................................................................................................. 336
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 349
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 350
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 352
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 354
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 357
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 359
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 360
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 361
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 363
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 364
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 365
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 366
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 367
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 368
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 369
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 370
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 371
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 372
Watchdog Timer ........................................................................................................................... 373
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 377
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 378
June 18, 201220
Texas Instruments-Production Data
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NRND: Not recommended for new designs.