Datasheet

5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
5.4 Register Map
Table 5-7 on page 188 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 5-7. System Control Register Map
See
page
DescriptionResetTypeNameOffset
190Device Identification 0-RODID00x000
206Device Identification 1-RODID10x004
208Device Capabilities 00x00FF.007FRODC00x008
209Device Capabilities 10x0111.32FFRODC10x010
211Device Capabilities 20x010F.1313RODC20x014
213Device Capabilities 30x830F.81FFRODC30x018
215Device Capabilities 40x5100.007FRODC40x01C
192Brown-Out Reset Control0x0000.7FFDR/WPBORCTL0x030
193LDO Power Control0x0000.0000R/WLDOPCTL0x034
238Software Reset Control 00x00000000R/WSRCR00x040
239Software Reset Control 10x00000000R/WSRCR10x044
241Software Reset Control 20x00000000R/WSRCR20x048
194Raw Interrupt Status0x0000.0000RORIS0x050
195Interrupt Mask Control0x0000.0000R/WIMC0x054
196Masked Interrupt Status and Clear0x0000.0000R/W1CMISC0x058
197Reset Cause-R/WRESC0x05C
198Run-Mode Clock Configuration0x078E.3AD1R/WRCC0x060
202XTAL to PLL Translation-ROPLLCFG0x064
203Run-Mode Clock Configuration 20x0780.2810R/WRCC20x070
217Run Mode Clock Gating Control Register 00x00000040R/WRCGC00x100
223Run Mode Clock Gating Control Register 10x00000000R/WRCGC10x104
232Run Mode Clock Gating Control Register 20x00000000R/WRCGC20x108
219Sleep Mode Clock Gating Control Register 00x00000040R/WSCGC00x110
226Sleep Mode Clock Gating Control Register 10x00000000R/WSCGC10x114
234Sleep Mode Clock Gating Control Register 20x00000000R/WSCGC20x118
June 18, 2012188
Texas Instruments-Production Data
System Control
NRND: Not recommended for new designs.