Datasheet

Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 123
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 123
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 125
Register 26: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 126
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 127
Register 28: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 130
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 131
Register 30: System Control (SYSCTRL), offset 0xD10 ....................................................................... 133
Register 31: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 135
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 137
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 138
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 139
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 140
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 144
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 150
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 151
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 152
Register 40: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 153
Register 41: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 154
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 156
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 157
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 157
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 157
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 157
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 159
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 159
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 159
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 159
System Control ............................................................................................................................ 175
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 190
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 192
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 193
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 194
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 195
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 196
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 197
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 198
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 202
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 203
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 205
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 206
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 208
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 209
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 211
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 213
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 215
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 217
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 219
June 18, 201218
Texas Instruments-Production Data
Table of Contents
NRND: Not recommended for new designs.