Datasheet

■ Local control, such as reset (see “Reset Control” on page 176), power (see “Power
Control” on page 180) and clock control (see “Clock Control” on page 181)
■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 186
5.2.1 Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
5.2.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
5.2.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
5.2.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion; see “External RST Pin” on page 177.
2. Power-on reset (POR); see “Power-On Reset (POR)” on page 177.
3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 178.
4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 179.
5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 179.
Table 5-3 provides a summary of results of the various reset operations.
Table 5-3. Reset Sources
On-Chip Peripherals Reset?JTAG Reset?Core Reset?Reset Source
YesYesYesPower-On Reset
YesPin Config OnlyYesRST
YesNoYesBrown-Out Reset
YesNoYesSoftware System Request
Reset
a
Yes
b
NoNoSoftware Peripheral Reset
YesNoYesWatchdog Reset
a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
June 18, 2012176
Texas Instruments-Production Data
System Control
NRND: Not recommended for new designs.