Datasheet

the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 4-5. Boundary Scan Register Format
O
TDOTDI
O
I
N E
U
T
O
O
I
N E
U
T
O
O
I
N E
U
T
O
O
I
N E
U
T
I
N
...
...
RSTGPIO PB6 GPIO m GPIO m+1 GPIO n
4.5.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
June 18, 2012174
Texas Instruments-Production Data
JTAG Interface
NRND: Not recommended for new designs.