Datasheet

4.1 Block Diagram
Figure 4-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
TRST
4.2 Signal Description
Table 4-1 on page 163 and Table 4-2 on page 164 list the external signals of the JTAG/SWD controller
and describe the function of each. The JTAG/SWD controller signals are alternate functions for
some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function.
The JTAG/SWD controller signals are under commit protection and require a special process to be
configured as GPIOs, see “Commit Control” on page 297. The column in the table below titled "Pin
Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL bit in
the GPIO Alternate Function Select (GPIOAFSEL) register (page 311) is set to choose the
JTAG/SWD function. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 289.
Table 4-1. JTAG_SWD_SWO Signals (100LQFP)
DescriptionBuffer Type
a
Pin TypePin NumberPin Name
JTAG/SWD CLK.TTLI80SWCLK
JTAG TMS and SWDIO.TTLI/O79SWDIO
JTAG TDO and SWO.TTLO77SWO
JTAG/SWD CLK.TTLI80TCK
JTAG TDI.TTLI78TDI
JTAG TDO and SWO.TTLO77TDO
JTAG TMS and SWDIO.TTLI/O79TMS
JTAG TRST.TTLI89TRST
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
163June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.