Datasheet

List of Tables
Table 1. Revision History .................................................................................................. 27
Table 2. Documentation Conventions ................................................................................ 35
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 61
Table 2-2. Processor Register Map ....................................................................................... 62
Table 2-3. PSR Register Combinations ................................................................................. 67
Table 2-4. Memory Map ....................................................................................................... 75
Table 2-5. Memory Access Behavior ..................................................................................... 77
Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 80
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 80
Table 2-8. Exception Types .................................................................................................. 85
Table 2-9. Interrupts ............................................................................................................ 86
Table 2-10. Exception Return Behavior ................................................................................... 91
Table 2-11. Faults ................................................................................................................. 92
Table 2-12. Fault Status and Fault Address Registers .............................................................. 93
Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 95
Table 3-1. Core Peripheral Register Regions ......................................................................... 98
Table 3-2. Memory Attributes Summary .............................................................................. 101
Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 104
Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 105
Table 3-5. AP Bit Field Encoding ........................................................................................ 105
Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 105
Table 3-7. Peripherals Register Map ................................................................................... 106
Table 3-8. Interrupt Priority Levels ...................................................................................... 131
Table 3-9. Example SIZE Field Values ................................................................................ 159
Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 163
Table 4-2. JTAG_SWD_SWO Signals (108BGA) ................................................................. 164
Table 4-3. JTAG Port Pins Reset State ............................................................................... 164
Table 4-4. JTAG Instruction Register Commands ................................................................. 171
Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 175
Table 5-2. System Control & Clocks Signals (108BGA) ........................................................ 175
Table 5-3. Reset Sources ................................................................................................... 176
Table 5-4. Clock Source Options ........................................................................................ 182
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 184
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 184
Table 5-7. System Control Register Map ............................................................................. 188
Table 5-8. RCC2 Fields that Override RCC fields ................................................................. 203
Table 6-1. Hibernate Signals (100LQFP) ............................................................................. 243
Table 6-2. Hibernate Signals (108BGA) .............................................................................. 244
Table 6-3. Hibernation Module Register Map ....................................................................... 250
Table 7-1. Flash Protection Policy Combinations ................................................................. 264
Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 267
Table 7-3. Flash Register Map ............................................................................................ 267
Table 8-1. GPIO Pins With Non-Zero Reset Values .............................................................. 290
Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 290
Table 8-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 291
Table 8-4. GPIO Signals (100LQFP) ................................................................................... 292
June 18, 201214
Texas Instruments-Production Data
Table of Contents
NRND: Not recommended for new designs.