Datasheet

Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 483
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 484
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 484
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 485
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 486
Figure 14-1. I
2
C Block Diagram ............................................................................................. 515
Figure 14-2. I
2
C Bus Configuration ........................................................................................ 516
Figure 14-3. START and STOP Conditions ............................................................................. 516
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 517
Figure 14-5. R/S Bit in First Byte ............................................................................................ 517
Figure 14-6. Data Validity During Bit Transfer on the I
2
C Bus ................................................... 517
Figure 14-7. Master Single SEND .......................................................................................... 521
Figure 14-8. Master Single RECEIVE ..................................................................................... 522
Figure 14-9. Master Burst SEND ........................................................................................... 523
Figure 14-10. Master Burst RECEIVE ...................................................................................... 524
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 525
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 526
Figure 14-13. Slave Command Sequence ................................................................................ 527
Figure 15-1. CAN Controller Block Diagram ............................................................................ 552
Figure 15-2. CAN Data/Remote Frame .................................................................................. 553
Figure 15-3. Message Objects in a FIFO Buffer ...................................................................... 562
Figure 15-4. CAN Bit Time .................................................................................................... 566
Figure 16-1. Ethernet Controller ............................................................................................. 599
Figure 16-2. Ethernet Controller Block Diagram ...................................................................... 599
Figure 16-3. Ethernet Frame ................................................................................................. 601
Figure 16-4. Interface to an Ethernet Jack .............................................................................. 607
Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 647
Figure 17-2. Structure of Comparator Unit .............................................................................. 648
Figure 17-3. Comparator Internal Reference Structure ............................................................ 649
Figure 18-1. PWM Unit Diagram ............................................................................................ 660
Figure 18-2. PWM Module Block Diagram .............................................................................. 661
Figure 18-3. PWM Count-Down Mode .................................................................................... 663
Figure 18-4. PWM Count-Up/Down Mode .............................................................................. 663
Figure 18-5. PWM Generation Example In Count-Up/Down Mode ........................................... 664
Figure 18-6. PWM Dead-Band Generator ............................................................................... 664
Figure 19-1. QEI Block Diagram ............................................................................................ 699
Figure 19-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 701
Figure 20-1. 100-Pin LQFP Package Pin Diagram .................................................................. 716
Figure 20-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 717
Figure 23-1. Load Conditions ................................................................................................ 752
Figure 23-2. JTAG Test Clock Input Timing ............................................................................. 754
Figure 23-3. JTAG Test Access Port (TAP) Timing .................................................................. 755
Figure 23-4. JTAG TRST Timing ............................................................................................ 755
Figure 23-5. External Reset Timing (RST) .............................................................................. 756
Figure 23-6. Power-On Reset Timing ..................................................................................... 756
Figure 23-7. Brown-Out Reset Timing .................................................................................... 756
Figure 23-8. Software Reset Timing ....................................................................................... 756
Figure 23-9. Watchdog Reset Timing ..................................................................................... 757
June 18, 201212
Texas Instruments-Production Data
Table of Contents
NRND: Not recommended for new designs.