Datasheet

List of Figures
Figure 1-1. Stellaris LM3S8962 Microcontroller High-Level Block Diagram ............................... 48
Figure 2-1. CPU Block Diagram ............................................................................................. 58
Figure 2-2. TPIU Block Diagram ............................................................................................ 59
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 61
Figure 2-4. Bit-Band Mapping ................................................................................................ 81
Figure 2-5. Data Storage ....................................................................................................... 82
Figure 2-6. Vector Table ........................................................................................................ 88
Figure 2-7. Exception Stack Frame ........................................................................................ 90
Figure 3-1. SRD Use Example ............................................................................................. 104
Figure 4-1. JTAG Module Block Diagram .............................................................................. 163
Figure 4-2. Test Access Port State Machine ......................................................................... 167
Figure 4-3. IDCODE Register Format ................................................................................... 173
Figure 4-4. BYPASS Register Format ................................................................................... 173
Figure 4-5. Boundary Scan Register Format ......................................................................... 174
Figure 5-1. Basic RST Configuration .................................................................................... 177
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 178
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 178
Figure 5-4. Power Architecture ............................................................................................ 181
Figure 5-5. Main Clock Tree ................................................................................................ 183
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 243
Figure 6-2. Clock Source Using Crystal ................................................................................ 245
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 246
Figure 7-1. Flash Block Diagram .......................................................................................... 263
Figure 8-1. GPIO Port Block Diagram ................................................................................... 295
Figure 8-2. GPIODATA Write Example ................................................................................. 296
Figure 8-3. GPIODATA Read Example ................................................................................. 296
Figure 9-1. GPTM Module Block Diagram ............................................................................ 337
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 342
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 343
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 344
Figure 10-1. WDT Module Block Diagram .............................................................................. 374
Figure 11-1. ADC Module Block Diagram ............................................................................... 398
Figure 11-2. Differential Sampling Range, V
IN_ODD
= 1.5 V ...................................................... 402
Figure 11-3. Differential Sampling Range, V
IN_ODD
= 0.75 V .................................................... 402
Figure 11-4. Differential Sampling Range, V
IN_ODD
= 2.25 V .................................................... 403
Figure 11-5. Internal Temperature Sensor Characteristic ......................................................... 404
Figure 12-1. UART Module Block Diagram ............................................................................. 435
Figure 12-2. UART Character Frame ..................................................................................... 436
Figure 12-3. IrDA Data Modulation ......................................................................................... 438
Figure 13-1. SSI Module Block Diagram ................................................................................. 476
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 479
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 480
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 480
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 481
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 482
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 482
11June 18, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S8962 Microcontroller
NRND: Not recommended for new designs.