Datasheet
In current Stellaris microcontroller implementations, the shareability and cache policy attributes do
not affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations.
3.1.4.3 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 75 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 144 for more information.
3.2 Register Map
Table 3-7 on page 106 lists the Cortex-M3 Peripheral SysTick, NVIC, MPU and SCB registers. The
offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-7. Peripherals Register Map
See
page
DescriptionResetTypeNameOffset
System Timer (SysTick) Registers
109SysTick Control and Status Register0x0000.0000R/WSTCTRL0x010
111SysTick Reload Value Register0x0000.0000R/WSTRELOAD0x014
112SysTick Current Value Register0x0000.0000R/WCSTCURRENT0x018
Nested Vectored Interrupt Controller (NVIC) Registers
113Interrupt 0-31 Set Enable0x0000.0000R/WEN00x100
114Interrupt 32-43 Set Enable0x0000.0000R/WEN10x104
115Interrupt 0-31 Clear Enable0x0000.0000R/WDIS00x180
116Interrupt 32-43 Clear Enable0x0000.0000R/WDIS10x184
117Interrupt 0-31 Set Pending0x0000.0000R/WPEND00x200
118Interrupt 32-43 Set Pending0x0000.0000R/WPEND10x204
119Interrupt 0-31 Clear Pending0x0000.0000R/WUNPEND00x280
120Interrupt 32-43 Clear Pending0x0000.0000R/WUNPEND10x284
121Interrupt 0-31 Active Bit0x0000.0000ROACTIVE00x300
122Interrupt 32-43 Active Bit0x0000.0000ROACTIVE10x304
123Interrupt 0-3 Priority0x0000.0000R/WPRI00x400
123Interrupt 4-7 Priority0x0000.0000R/WPRI10x404
123Interrupt 8-11 Priority0x0000.0000R/WPRI20x408
123Interrupt 12-15 Priority0x0000.0000R/WPRI30x40C
123Interrupt 16-19 Priority0x0000.0000R/WPRI40x410
June 18, 2012106
Texas Instruments-Production Data
Cortex-M3 Peripherals
NRND: Not recommended for new designs.