Datasheet

EN
FLAG1
T
D1
Input Supply
(2.7V - 5.5V)
VCC
LM3881
FLAG1
GND
C
ADJ
EN
FLAG3
FLAG2
INV
TADJ
R
EN1
R
EN2
¸
¹
·
¨
©
§
R
EN1
VCC
ENABLE
= 1.22V
1 +
R
EN2
- 7 PA (R
EN1
llR
EN2
)
LM3881
SNVS555C –JANUARY 2008–REVISED APRIL 2013 www.ti.com
A resistor divider can also be used to enable the LM3881 based on exceeding a certain VCC supply voltage
threshold. Care needs to be taken when sizing the resistor divider to include the effects of the internal EN pull-up
current source. The supply voltage for which EN is asserted is given by
Figure 16. Enable Based On Input Supply Level
One of the features of the enable pin is that it provides glitch free operation. The timer will start counting at a
rising threshold, but will always reset if the enable pin is de-asserted before the first output flag is released. This
is illustrated in the timing diagram below, assuming INV is low.
Figure 17. Enable Glitch Timing, INV Low
If the EN pin remains high for the entire power up sequence, then the part will operate as shown in the standard
timing diagrams. However, if the EN signal is de-asserted before the power-up sequence is completed, the part
will enter a controlled shutdown. This allows the system to initiate a controlled power sequence, preventing any
latch conditions to occur. The following timing diagrams describe the flag sequence if the EN pin is de-asserted
after FLAG1 releases, but before the entire power-up sequence is completed. INV is assumed low.
10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM3881