Datasheet

V
PP-RMS
= V
PP-C
2
+ V
PP-ESR
2
V
OUT
=
V
PP-ESR
= I
PP
* R
ESR
V
PP-C
=
I
ripple
f x 4 x C
LM3674
SNVS405F –DECEMBER 2005–REVISED MAY 2013 www.ti.com
The output voltage ripple is caused by the charging and discharging of the output capacitor and by the R
ESR
and
can be calculated as:
Voltage peak-to-peak ripple due to capacitance can be expressed as follow:
(11)
Voltage peak-to-peak ripple due to ESR =
(12)
Because these two components are out of phase the rms value can be used to get an approximate value of
peak-to-peak ripple.
Voltage peak-to-peak ripple, root mean squared =
(13)
Note that the output ripple is dependent on the current ripple and the equivalent series resistance of the output
capacitor (R
ESR
).
The R
ESR
is frequency dependent (as well as temperature dependent); make sure the value used for calculations
is at the switching frequency of the part.
Table 3. Suggested Capacitors and Their Suppliers
Model Type Vendor Voltage Rating Case size inch (mm)
10 µF for C
OUT
GRM21BR60J106K Ceramic, X5R Murata 6.3V 0805 (2012)
C2012X5R0J106K Ceramic, X5R TDK 6.3V 0805 (2012)
JMK212BJ106K Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012)
4.7 µF for C
IN
GRM21BR60J475K Ceramic, X5R Murata 6.3V 0805 (2012)
JMK212BJ475K Ceramic, X5R Taiyo-Yuden 6.3V 0805 (2012)
C2012X5R0J475K Ceramic, X5R TDK 6.3V 0805 (2012)
BOARD LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or
instability.
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