Datasheet
DAP
11
12
10
9
8
7
6
5
4
3
2
1
FB
VSEL
MODE/
SYNC
SGND
NC
SVDD
VOUT
SW2
PGND
SW1
PVDD
EN
1
2
3
4
9
10
11
12
8
DAP
5
7
6
VOUT
SW2
PGND
SW1
PV
IN
EN
FB
VSEL
MODE/
SYNC
SGND
NC*
VDD
Pin Descriptions
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NOTE: The above figures are not to any actual scale.
5 Pin Descriptions
Pin No Pin Name Description
1 V
OUT
Connect to output capacitor.
2 SW2 Switching Node connection to the internal PFET switch (P2) and NFET synchronous rectifier (N2).
3 PGND Power Ground.
4 SW1 Switching Node connection to the internal PFET switch (P1) and NFET synchronous rectifier (N1).
5 PV
IN
Supply to the power switch, connect to the input capacitor.
6 EN Enable Input. Set this digital input high for normal operation. For shutdown, set low.
7 V
DD
Signal Supply input. If board layout is not optimum an optional 1µF ceramic capacitor is
suggested as close to this pin as possible.
8 NC No connect. Connect this pin to SGND on PCB layout.
9 SGND Analog and Control Ground.
10 MODE/SYNC Mode = LOW, Automatic Mode. Mode= HI, Forced PWM Mode SYNC = external clock
synchronization from 1.6MHz to 2.7MHz (When SYNC function is used, device is forced in PWM
mode).
11 VSEL Voltage selection pin; (i.e., 2.8 V/3.3 V option) Logic input low = 2.8 V and logic high = 3.3 V to
set output Voltage.
12 FB Feedback Analog Input. Connect to the output at the output filter.
DAP DAP Die Attach Pad, connect the DAP to SGND on PCB layout to enhance thermal performance. It
should not be used as a primary ground connection.
6 Bill Of Materials
Component Name Manufacturer Specification Case Size
LM3668 TI WSON-12 3 mm x 3 mm x 0.8 mm
C
IN
= 10 µF JMK212BJ106K 0805(2012)
C
OUT
= 22 µF (2.8 V/3.3 V, 3.0 V/3.4 JK212BJ226MG 0805(2012)
V)
Taiyo-Yuden
C
OUT
= 22 µF (4.5 V/5.0 V) LMK212BJ226MMG 0805(2012)
C
IN
_ V
DD
= 4.7 µF JMK212BJ475M 0805(2012)
Inductor Coilcraft LPS4018–222L 4mm x 4mm x 1.8mm
2
AN-1623 LM3668 Evaluation Board SNVA236F–June 2007–Revised April 2013
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