Datasheet

LM2578A, LM3578A
www.ti.com SNVS767E –AUGUST 2000–REVISED APRIL 2013
Electrical Characteristics
These specifications apply for 2V ≤ V
IN
≤ 40V (2.2V ≤ V
IN
≤ 40V for T
J
≤ −25°C), timing capacitor C
T
= 3900 pF, and 25% ≤
duty cycle ≤ 75%, unless otherwise specified. Values in standard typeface are for T
J
= 25°C; values in boldface type apply
for operation over the specified operating junction temperature range.
Typical
(1)
LM2578A/
Symbol Parameter Conditions LM3578A Units
Limit
(2)
OSCILLATOR
f
OSC
Frequency 20 kHz
24 kHz (max)
16 kHz (min)
Δf
OSC
/ΔT Frequency Drift with Temperature −0.13 %/°C
Amplitude 550 mV
p-p
REFERENCE/COMPARATOR
(3)
V
R
Input Reference I
1
= I
2
= 0 mA and 1.0 V
Voltage
I
1
= I
2
= 1 mA ±1%
(4)
1.050/1.070 V (max)
0.950/0.930 V (min)
ΔV
R
/ΔV
IN
Input Reference Voltage Line I
1
= I
2
= 0 mA and 0.003 %/V
Regulation
I
1
= I
2
= 1 mA ±1%
(4)
0.01/0.02 %/V (max)
I
INV
Inverting Input Current I
1
= I
2
= 0 mA, duty cycle = 25% 0.5 μA
Level Shift Accuracy Level Shift Current = 1 mA 1.0 %
10/13 % (max)
ΔV
R
/Δt Input Reference Voltage Long Term 100 ppm/1000h
Stability
OUTPUT
V
C
(sat) Collector Saturation Voltage I
C
= 750 mA pulsed, Emitter 0.7 V
grounded
0.90/1.2 V (max)
V
E
(sat) Emitter Saturation Voltage I
O
= 80 mA pulsed, 1.4 V
V
IN
= V
C
= 40V 1.7/2.0 V (max)
I
CES
Collector Leakage Current V
IN
= V
CE
= 40V, Emitter grounded, 0.1 μA
Output OFF
200/250 μA (max)
BV
CEO(SUS)
Collector-Emitter Sustaining Voltage I
SUST
= 0.2A (pulsed), V
IN
= 0 60 V
50 V (min)
CURRENT LIMIT
V
CL
Sense Voltage Shutdown Level Referred to V
IN
or Ground 110 mV
See
(5)
80 mV (min)
160 mV (max)
ΔV
CL
/ΔT Sense Voltage Temperature Drift 0.3 %/°C
I
CL
Sense Bias Current Referred to V
IN
4.0 μA
Referred to ground 0.4 μA
(1) Typical values are for T
J
= 25°C and represent the most likely parametric norm.
(2) All limits specified at room temperature (standard type face) and at temperature extremes (bold type face). Room temperature limits are
100% production tested. Limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate AOQL.
(3) Input terminals are protected from accidental shorts to ground but if external voltages higher than the reference voltage are applied,
excessive current will flow and should be limited to less than 5 mA.
(4) I
1
and I
2
are the external sink currents at the inputs (refer to Test Circuit).
(5) Connection of a 10 kΩ resistor from pin 1 to pin 4 will drive the duty cycle to its maximum, typically 90%. Applying the minimum Current
Limit Sense Voltage to pin 7 will not reduce the duty cycle to less than 50%. Applying the maximum Current Limit Sense Voltage to pin 7
is certain to reduce the duty cycle below 50%. Increasing this voltage by 15 mV may be required to reduce the duty cycle to 0%, when
the Collector output swing is 40V or greater (see Ground-Referred Current Limit Sense Voltage typical curve).
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