Datasheet

1
8
2
3
7
6
5
8
10
4 9
1 7
SDA
SCL
AS W
.
A A
PRS R A
From Master to Slave
From Slave to Master
Data- Data
( 8 bits)
- ACKNOWLEDGE
- START CONDITION
- STOP CONDITION
- REPEATED START CONDITION
- WRITE
- READ
A
S
RS
P
W
R
Slave Address
( 7 bits)
Control Register Add
( 8 bits)
Slave Address
( 7 bits)
LM3549
www.ti.com SNVS640A –AUGUST 2010–REVISED MAY 2013
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in
Figure 24
Figure 24. I
2
C Read Cycle
Figure 25. I
2
C Timing Diagram
Table 1. I
2
C Timing Parameters
Limit
Symbol Parameter Units
Min Max
1 Hold Time (repeated) START Condition 0.6 µs
2 Clock Low Time 1.3 µs
3 Clock High Time 600 ns
4 Setup Time for a Repeated START Condition 600 ns
5 Data Hold 300 900 ns
5 Data Hold Time (input direction) 0 900 ns
6 Data Setup Time 100 ns
7 Rise Time of SDA and SCL 20 + 0.1Cb 300 ns
8 Fall Time of SDA and SCL 15 + 0.1Cb 300 ns
9 Set-up Time for STOP condition 600 ns
10 Bus Free Time between a STOP and a START Condition 1.3 µs
Cb Capacitive Load for Each Bus Line 10 200 pF
Register Map
ADDR NAME D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT NOTE
00H BANK_SEL Bank_sel[1:0] 00H EEPROM
01H IR0_LSB Red 0 [7:0] 81H EEPROM
02H IR0_MSB N/A Red 0 [9:8] 01H EEPROM
03H IG0_LSB Green 0 [7:0] 81H EEPROM
04H IG0_MSB N/A Green 0 [9:8] 01H EEPROM
05H IB0_LSB Blue 0 [7:0] 81H EEPROM
06H IB0_MSB N/A Blue 0 [9:8] 01H EEPROM
07H IR1_LSB Red 1 [7:0] E7H EEPROM
08H IR1_MSB N/A Red 1 [9:8] 00H EEPROM
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