Datasheet

LM2524D, LM3524D
SNVS766E –JUNE 2009–REVISED MAY 2013 www.ti.com
So far it is assumed η = 100%, where the actual efficiency or η
MAX
will be somewhat less due to the saturation
voltage of Q1 and forward on voltage of D1. The internal power loss due to these voltages is the average I
L
current flowing, or I
IN
, through either V
SAT
or V
D1
. For V
SAT
= V
D1
= 1V this power loss becomes I
IN(DC)
(1V). η
MAX
is then:
(21)
(22)
This equation assumes only DC losses, however η
MAX
is further decreased because of the switching time of Q1
and D1.
In calculating the output capacitor C
o
it can be seen that C
o
supplies I
o
during t
ON
. The voltage change on C
o
during this time will be some ΔV
c
= ΔV
o
or the output ripple of the regulator. Calculation of C
o
is:
(23)
where: C
o
is in farads, f is the switching frequency,
ΔV
o
is the p-p output ripple
Calculation of inductor L1 is as follows:
(24)
V
IN
is applied across L1
(25)
where: L1 is in henrys, f is the switching frequency in Hz
To apply the above theory, a complete step-up switching regulator is shown in Figure 30. Since V
IN
is 5V, V
REF
is
tied to V
IN
. The input voltage is divided by 2 to bias the error amplifier's inverting input. The output voltage is:
(26)
The network D1, C1 forms a slow start circuit.
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