Datasheet

P
IN
=
I
2
rms-IN
x ESR
n
I
rms-IN
= I
O
x
D(1 - D)
I
rms-IN
= 10 x
0.1(0.9)
= 3A
LM3495
www.ti.com SNVS410F –FEBRUARY 2006–REVISED APRIL 2013
Input Capacitor Loss
This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this
equation ‘n’ is the number of capacitors in parallel.
(48)
P
IN
= (3A)
2
x 2mΩ) = 0.018W (49)
Output Inductor Loss
P
LOUT
=(I
O
)
2
x R
L
(50)
P
LOUT
= (10A)
2
x 3 mΩ = 0.3W (51)
Total Loss
P
LOSS
= 1.53W (52)
Efficiency
n = 12W/(12W +1.50W) = 88% (53)
Layout Considerations
To produce an optimal power solution with the LM3495, good layout and design of the PCB are as important as
the component selection. The following are several guidelines to aid in creating a good layout.
KELVIN TRACES FOR SENSE LINES
The pins of the low-side FET should be connected as close as possible to the SW/CSH and CSL pins. Each pin
should use a separate trace, and the traces should be run parallel to each other to give common mode rejection.
Although it can be difficult in a compact design, these traces should stay away from the output inductor if
possible, to avoid coupling stray flux.
The SNS pin should also be connected using a separate Kelvin trace, running from the positive pin/pad of the
output cap to the pin itself. This trace should also be used to connect to the top of the feedback resistors. Keep
this trace away from the switch node and from the output inductor.
SEPARATE PGND AND SGND
Good layout techniques include a dedicated ground plane, usually on an internal layer. Signal level components
like the compensation and feedback resistors should be connected to a section of this internal plane, SGND. The
SGND section of the plane should be connected to the power ground at only one point. The best place to
connect the SGND and PGND is right at the SGND pin.
MINIMIZE THE SWITCH NODE
The plane that connects the power FETs and output inductor together radiates more EMI as it gets larger. Use
just enough copper to give low impedance to the switching currents.
LOW IMPEDANCE POWER PATH
The power path includes the input capacitors, power FETs, output inductor, and output capacitors. Keep these
components on the same side of the PCB and connect them with thick traces or copper planes (shapes) on the
same layer. Vias add resistance and inductance to the power path, and have high impedance connections to
internal planes than to the top of bottom layers of a PCB. If heavy switching currents must be routed through vias
and/or internal planes, use multiple vias in parallel to reduce their resistance and inductance. The power
components should be kept close together. The longer the paths that connect them, the more they act as
antennas, radiating unwanted EMI.
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