Datasheet

L
MIN1
=
x D
V
IN(MAX)
- V
O
f
SW
x 'i
O
LM3495
SNVS410F –FEBRUARY 2006–REVISED APRIL 2013 www.ti.com
MOSFETS
Selection of the power FETs is governed by the same tradeoffs as switching frequency. Breaking down the
losses in the high-side and low-side FETs is one way to determine relative efficiencies between different FETs.
When using discrete SO-8 FETs the LM3495 is most efficient for output currents of 2A to 10A.
Losses in the power FETs can be broken down into conduction loss, gate charging loss, and switching loss.
Conduction, or I
2
R loss, P
C
, is approximately:
P
C
= D (I
O
2
x R
DSON-HI
x 1.3) (High-Side MOSFET) (11)
P
C
= (1 - D) x (I
O
2
x (R
DSON-LO
x 1.3 + R
SNS
)) (Low-Side MOSFET) (12)
In the above equations R
DSON-HI
and R
DSON-LO
refer to on-resistance of the high-side and low-side FETs,
respectively. R
SNS
is 0 if it is not used. The factor 1.3 accounts for the increase in FET on-resistance due to
heating. Alternatively, the factor of 1.3 can be ignored and the on-resistance of the FET can be estimated using
the R
DSON
vs Temperature curves in the FET datasheets. Gate charging loss, P
GC
, results from the current
driving the gate capacitance of the power FETs and is approximated as:
P
GC
= n x (V
LIN5
– V
D
) x Q
G-HI
x f
SW
(High-Side MOSFET) (13)
P
GC
= n x V
LIN5
x Q
G-LO
x f
SW
(Low-Side MOSFET) (14)
In the above equations Q
G-HI
and Q
G-LO
refer to the gate charge of the high-side and low-side FETs, respectively.
The factor ‘n’ is the number of FETs (if multiple devices have been placed in parallel) and Q
G
is the total gate
charge of the FET. If different types of FETs are used, the ‘n’ term can be ignored and their gate charges
summed to form a cumulative Q
G
. Gate charge loss differs from conduction and switching losses in that the
actual dissipation occurs in the LM3495 and not in the FET itself. Further loss in the LM3495 is incurred as the
gate driving current passes through the internal linear regulator. This loss term is factored into the Chip
Operating Loss portion of the Efficiency Calculations section.
Switching loss, P
SW
, occurs during the brief transition period as the FET turns on and off. During the transition
period both current and voltage are present in the channel of the FET. The loss can be approximated as:
P
SW
= 0.5 x V
IN
x I
O
x (t
R
+ t
F
) x f
SW
(15)
Where t
R
and t
F
are the rise and fall times of the FET. Switching loss is calculated for the high-side FET only.
Switching loss in the low-side FET is negligible because the body diode of the low-side FET turns on before the
FET itself, minimizing the voltage from drain to source before turn-on.
For this example, the maximum drain-to-source voltage applied to either FET is 13.2V. The maximum drive
voltage at the gate of the high-side FET is 4.5V, and the maximum drive voltage for the low-side FET is 5V. Any
FET selected must be able to withstand 13.2V plus any ringing from drain to source, and be able to handle at
least 5V plus ringing from gate to source. One good choice of FET for the high-side has an R
DSON
of 9.6 mΩ,
total gate charge Q
G
of 11 nC, and rise and fall times of 5 and 8 ns, respectively. For the low-side FET, a good
choice has an R
DSON
of 3.4 mΩ and gate charge of 33 nC. These values have been taken from the FET
datasheets with a V
GS
of 4.5V.
OUTPUT INDUCTOR
The first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value is
based on the desired ripple current, Δi
O
, which flows in the inductor along with the load current. This ripple
current will flow through the ESR and impedance of the output capacitor to create the output voltage ripple, Δv
O
.
Due to the unique control architecture of the LM3495, a second requirement for minimum inductance must be
used based on the R
DSON
of the low-side FET and the desired switching frequency. As with switching frequency,
the inductance used is a tradeoff between size and cost. Larger inductance means low current ripple and hence
low output voltage ripple. However, less inductance results in smaller, less expensive devices. An inductance
that gives a ripple current of 30% to 40% of the maximum load current is a good starting point (Δi
O
= 30% to
40%*I
O
). Minimum inductance should be calculated from this value, using the maximum input voltage, as:
(16)
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