Datasheet

D =
V
O
V
IN
D
CLAMP
= 3.2 x
V
O
V
IN
LM3495
www.ti.com SNVS410F –FEBRUARY 2006–REVISED APRIL 2013
PARALLEL LOW-SIDE SCHOTTKY DIODE
Many synchronous buck regulators include a Schottky diode in parallel with the low-side power FET. The low
forward drop and short reverse recovery time of Schottky diodes can improve efficiency by preventing the FET's
body diode from turning on. This technique is most effective in circuits with output currents of 5A or less. The
parallel Schottky diode must be placed as close as possible to the power FET to prevent trace inductance from
negating the gains in efficiency.
ADAPTIVE DUTY CYCLE CLAMP
The adaptive duty cycle clamp is an extra layer of protection used during high current conditions or large load
transients. When a high-side pulse is skipped due to current limit, the output voltage tends to decrease rapidly.
The steady state control loop of the LM3495 responds by commanding a higher duty cycle at the next high-side
turn-on. The result is a combination of high voltage across the output inductor and long duty cycles that could
result in inductor saturation. The adaptive duty cycle clamp prevents inductor saturation by providing a dynamic
maximum duty cycle, D
CLAMP
. The clamp is based on the sensed input and output voltages. D
CLAMP
can be
predicted with the following equation:
(8)
D
CLAMP
cannot exceed 100% (9)
SHUTDOWN
The LM3495 can be put into a low power shutdown mode by bringing the voltage at the COMP/SD pin below
0.3V. A signal-level BJT or FET can be controlled by most CMOS or TTL logic signals to perform this function.
The collector-to-emitter or drain-to-source capacitance should be less than 20 pF to minimize the effect on the
control loop compensation. During shutdown, both the high-side and low-side FETs are disabled. The output
voltage is discharged through the SNS pin by an internal 500Ω FET.
THERMAL SHUTDOWN
The LM3495 will enter a thermal shutdown state if the die temperature exceeds 150°C. Both the high-side and
low-side power FETs are turned off, the output voltage is discharged through an internal 500Ω FET, and the IC
will remain in this condition until the die temperature has dropped to approximately 135°C. At this point the
LM3495 will perform a soft-start.
Design Considerations
The most common circuit controlled by the LM3495 is a non-isolated, synchronous buck regulator. The buck
regulator steps down the input voltage and has a duty cycle, D, of:
(10)
The following is a design procedure for selecting all the components in the Typical Application circuit on the front
page. This circuit delivers a 1.2V ± 1% output voltage at output currents up to 10A from an input voltage of 12V ±
10%. This circuit is typical of a point-of-load (POL) module. A BOM for this typical application is listed in Table 3
at the end of this datasheet.
SWITCHING FREQUENCY
The selection of switching frequency is based on the tradeoffs between size, cost, and efficiency. In general, a
lower frequency means larger, more expensive inductors and capacitors will be needed. A higher switching
frequency generally results in a smaller but less efficient solution, as the power FET gate capacitances must be
charged and discharged more often in a given amount of time. For this application, a frequency of 500 kHz was
selected because the space on a POL circuit board is limited. This frequency is a good compromise between the
size of the inductor and FETs, transient response, and efficiency. Following the equation given for R
FRQ
in the
Applications Information section, a 54.9 kΩ 1% resistor should be used to switch at 500 kHz.
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