Datasheet

LG
SW/CSH
HG
BOOST
LM3495
D1
C
BOOT
VLIN5
L1
Q1
Q2
V
IN
+
Co
FREQ/SYNC
LM3495
External
Clock
100 pF
R
FRQ
C
SYNC
LM3495
SNVS410F –FEBRUARY 2006–REVISED APRIL 2013 www.ti.com
If the external clock fails low, timeout circuits will prevent the high-side FET from staying off for longer than 1.5
times the switching period (Switching period T
SW
= 1/f
SW
). At the end of this timeout period the regulator will
begin to switch at the frequency set by R
FRQ
.
If the external clock fails high, timeout circuits will again prevent the high-side FET from staying off longer than
1.5 times the switching period. After this timeout period, the internal oscillator takes over and switches at a fixed
1 MHz until the voltage on the FREQ/SYNC pin has decayed to approximately 0.6V. This decay follows the time
constant of C
SYNC
and R
FRQ
, and once it is complete the regulator will switch at the frequency set by R
FRQ
.
Care must be taken to prevent errant pulses from triggering the synchronization circuitry. In applications that will
not synchronize to an external clock, C
SYNC
should be connected from the FREQ/SYNC pin to signal ground as a
noise filter. When a clock pulse is first detected, the LM3495 begins switching at the external clock frequency.
Noise or a short burst of clock pulses can result in off times as long as 7.5 µs for the high-side FET if they occur
while the internal synchronization circuits are adjusting.
Figure 33. Clock Synchronization Circuit
MOSFET GATE DRIVE
The LM3495 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Power for
the high-side driver is supplied through the BOOST pin. For the high-side gate drive to fully turn on the top FET,
the BOOST pin voltage must be at least one threshold voltage, V
GS(th)
, greater than V
IN
. This voltage is supplied
from a local charge pump structure which consists of a Schottky diode and 0.1 µF capacitor, shown in Figure 34.
Both the bootstrap and the low-side FET driver are fed from VLIN5, which is the output of a 4.7V internal linear
regulator. This regulator has a dropout voltage of approximately 1V. If V
IN
drops below 4V, an internal switch
shorts the VIN and VLIN5 pins together. The drive voltage for the top FET driver is therefore VLIN5-V
D
, where V
D
is the drop across the Schottky diode D1. This information is needed to select the type of MOSFETs to be used.
Figure 34. Bootstrap Circuit
INPUT VOLTAGE BELOW 5.5V
The LM3495 includes an internal 4.7V linear regulator connected from the VIN pin to the VLIN5 pin. This linear
regulator feeds the logic and FET drive circuitry. For input voltages less than 5.5V, the VIN and VLIN5 pins can
be shorted together externally. The external short circuit bypasses both the internal linear regulator and the
internal PMOS switch, allowing the full input voltage to be used for driving the power FETs and minimizing
conduction loss in the LM3495 itself. For voltage inputs that range above and below 5.5V the LM3495 must not
use a short from VIN to VLIN5.
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