Datasheet

R
FRQ
=
f
SW
- 48.4
25.26 x 10
3
k:, f
SW
in kHz
V
O
= 0.6V x
R
FB1
R
FB1
+ R
FB2
LM3495
www.ti.com SNVS410F –FEBRUARY 2006–REVISED APRIL 2013
FPWM MODE OPERATION
The LM3495 operates under forced PWM when the FPWM pin is connected to ground. While in FPWM
operation, the LM3495 controls the output voltage by adjusting the duty cycle of the power FETs with trailing
edge PWM. The output inductor and capacitor filter the square wave produced as the power FETs chop the input
voltage, thereby creating a regulated output voltage. The DC level of the output voltage can be set anywhere
from 0.6V up to 5.5V, and is determined by a pair of feedback resistors using the following equation:
(3)
In steady state FPWM mode, the inductor current can flow from the drain to the source of the low-side FET,
keeping the converter in continuous conduction mode (CCM) at all times. CCM has the advantage of constant
frequency and nearly constant duty cycle (D = V
O
/V
IN
) over all load conditions, and it allows the converter to sink
current at the output if needed.
The switching frequency of the internal oscillator is set by a resistor, R
FRQ
, connected from the FREQ/SYNC pin
to ground. The proper resistor for a desired switching frequency, f
SW
, can be determined by using the following
equation:
(4)
SKIP MODE OPERATION
If the FPWM pin is left open-circuited, the LM3495 can enter into SKIP mode operation, delivering better
efficiency at light loads. As long as the inductor current is positive (flowing from the switch node to the output
node), SKIP mode is identical to FPWM mode. Once the inductor current becomes negative, however, an
internal zero-cross comparator will disable the low-side FET. This 'diode-emulation' mode allows the converter to
operate in discontinuous conduction mode (DCM). In DCM, the duty cycle decreases as the load current
decreases. A minimum on-time comparator prevents the duty cycle during DCM from decreasing below 80% of
the steady state duty cycle, D. The converter will allow one on-time pulse, causing the output voltage to rise and
the COMP/SD voltage to droop. If COMP/SD drops below the skip cycle comparator threshold of 1.05V, the
control logic will disable the high-side FET for one cycle, effectively skipping a pulse. This skipping action
continues until the COMP/SD voltage rises above the skip cycle threshold. Multiple pulses can be skipped
depending on load, input voltage, and output voltage. Switching frequency is not fixed during SKIP Mode, but
energy is saved because the high and low-side FETs are driven less frequently than in FPWM mode. In SKIP
mode the regulator cannot sink current at the output.
SKIP TO FPWM TRANSITION
The LM3495 employs circuitry to transition from SKIP mode to FPWM mode with minimal discontinuity in
inductor current and output voltage. When the FPWM pin is grounded, the threshold of the zero-cross
comparator decreases from 0V to -9.9 mV over fifteen switching cycles. After fifteen cycles have elapsed, the
zero-cross comparator is disabled entirely and the circuit switches to FPWM mode.
Note that "on-the-fly" changes from FPWM mode to SKIP mode are not recommended due to the possibility of
discontinuity in the inductor current and/or output voltage.
FREQUENCY SYNCHRONIZATION
The switching action of the LM3495 can be synchronized to external clocks or other fixed frequency signals in
the range of 200 kHz to 1.5 MHz. The external clock should be applied through a 100 pF coupling capacitor,
C
SYNC
, as shown in Figure 33. In order for the LM3495 to synchronize properly, the external clock should exceed
1.2V on each rising edge and remain above 1.2V for at least 100 ns.
The external clock should also fall below 0.3V on each falling edge, and remain below 0.3V for at least 100 ns.
Circuits that use an external clock should still have a resistor, R
FRQ
, connected from the FREQ/SYNC pin to
signal ground. R
FRQ
should be selected using the equation from FPWM MODE OPERATION to match the
external clock frequency. This allows the regulator to continue operating at approximately the same switching
frequency if the external clock fails and the coupling capacitor on the clock side is grounded or pulled to a logic
high.
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