LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 LM3495 Emulated Peak Current Mode Buck Controller for Low Output Voltage Check for Samples: LM3495 FEATURES DESCRIPTION • • • • The LM3495 is a PWM buck regulator which implements a unique emulated peak current mode control. This control method eliminates the switching noise which typically limits current mode operation at extremely short duty cycles and high operating frequency.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Connection Diagram BOOST 1 16 PGND HG 2 15 LG SW/CSH 3 14 VLIN5 CSL 4 13 VIN ILIM 5 12 SGND FPWM 6 11 COMP/SD SNS 7 10 FB FREQ/SYNC 8 9 TRACK LM3495 Figure 1. 16-Lead Plastic TSSOP Package (Top View) See Package Number PW0016A θJA = 155°C/W PIN DESCRIPTIONS BOOST (Pin 1): Supply rail for the high-side FET gate drive.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN, ILIM −0.3V to 20V SW/CSH (3) −0.5V to 20V BOOST, HG −0.3V to 25V BOOST to SW −0.3V to 6V FB −0.3V to 2V TRACK, FREQ, FPWM, VLIN5, SNS, LG, CSL −0.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise indicated, VIN = 12V.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Electrical Characteristics (continued) Specifications with standard type are for TJ = 25°C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise indicated, VIN = 12V.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics VIN = 12V unless specified, TA = 25°C unless specified. 6 FB Reference Voltage vs Temperature Switching Frequency vs Temperature Figure 2. Figure 3. VLIN5 Voltage vs Temperature Error Amplifier Transconductance vs Temperature Figure 4. Figure 5. VLIN5 Voltage vs VIN Efficiency in SKIP Mode VO = 2.2V, IO = 10 mA to 500 mA BOM in Table 2 Figure 6. Figure 7.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. Efficiency in FPWM Mode VO = 1.0V, IO = 0.5A to 7A BOM in Table 1 Efficiency in FPWM Mode VO = 2.2V, IO = 0.5A to 7A BOM in Table 2 Figure 8. Figure 9. Load Transient Response VIN = 3.3V, VO = 2.2V BOM in Table 2 Load Transient Response VIN = 12V, VO = 1.0V BOM in Table 1 Figure 10. Figure 11.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. 8 Soft-Start in FPWM Mode VIN = 12V, VO = 1.0V, IO = 5A BOM in Table 1 Soft-Start in FPWM Mode VIN = 3.3V, VO = 2.2V, IO = 5A BOM in Table 2 Figure 14. Figure 15. Soft-Start with Output Pre-bias VIN = 12V, VO = 1.0V, IO = 0A BOM in Table 1 Soft-Start with Output Pre-bias VIN = 3.3V, VO = 2.2V, IO = 0A BOM in Table 2 Figure 16.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. FA to SYNC Transition Clock Starts on Logic Low BOM in Table 1 FA to SYNC Transition Clock Starts on Logic High BOM in Table 1 Figure 20. Figure 21. SYNC to FA Transition Clock Ends on Logic Low BOM in Table 1 SYNC to FA Transition Clock Ends on Logic High BOM in Table 1 Figure 22. Figure 23.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) VIN = 12V unless specified, TA = 25°C unless specified. 10 Tracking With Equal Slew Rate VIN = 12V, VO = 1.0V, No Load BOM in Table 1 Tracking With Equal Slew Rate VIN = 5V, VO = 2.2V, No Load BOM in Table 2 Figure 26. Figure 27. SKIP to FPWM Transition VIN = 12V, VO = 1.0V, IO = 5A BOM in Table 1 fSW vs RFRQ VIN = 12V, VO = 1.0V, No Load BOM in Table 1 Figure 28. Figure 29.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Typical Application Circuit CF 1 F D1 CDD VIN = 12V ± 10% 2.2 F MODE FPWM VIN VLIN5 BOOST CB FREQ/SYNC CSYNC 100 pF RFRQ SW/CSH TRACK RILIM CC L1 VO = 1.2V, 10A ILIM 3.32 k LG 1 H Q2 10 m CO COMP/SD 1.5 k 22 F 25V Q1 HG LM3495 RC CIN 54.9 k VLIN5 Shutdown Signal 0.1 F 25V CINX 0.1 F 10 nF CSL 2 x 100 F 6.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Block Diagram TRACK VLIN5 VIN INTERNAL 4.7V REGULATOR INTERNAL SOFTSTART VREF = 0.6V BOOST FROM LG IRAMP SHOOTTHROUGH PROTECT FB IFREQ + + + - RAMP GENERATOR AND SLOPE COMPENSATION EA gm HICCUP HG COMP /SD - SW/ CSH - + + x4 CLAMPED: LO 0.9V HI 2.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 APPLICATIONS INFORMATION THEORY OF OPERATION The LM3495 is an advanced, current mode PWM synchronous controller. Unlike traditional peak current mode controllers which sense the current while the high-side FET is on, the LM3495 senses current while the low-side FET is on. The LM3495 then emulates the peak current waveform and uses that information to regulate the output voltage.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com One way to use the tracking feature is to design the tracking resistor divider so that the master supply output voltage (VOUT1) and the LM3495 output voltage (VOUT2) both rise together and reach their target values at the same time. For this case, the equation governing the values of the tracking divider resistors RT1 and RT2 is: RT1 0.65V = VOUT1 RT1 + RT2 (1) The above equation is set equal to 0.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 FPWM MODE OPERATION The LM3495 operates under forced PWM when the FPWM pin is connected to ground. While in FPWM operation, the LM3495 controls the output voltage by adjusting the duty cycle of the power FETs with trailing edge PWM. The output inductor and capacitor filter the square wave produced as the power FETs chop the input voltage, thereby creating a regulated output voltage.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com If the external clock fails low, timeout circuits will prevent the high-side FET from staying off for longer than 1.5 times the switching period (Switching period TSW = 1/fSW). At the end of this timeout period the regulator will begin to switch at the frequency set by RFRQ. If the external clock fails high, timeout circuits will again prevent the high-side FET from staying off longer than 1.5 times the switching period.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 UNDER VOLTAGE LOCK-OUT The 2.6V turn-on threshold on the voltage at VIN has a built in hysteresis of 300 mV. If input voltage drops below 2.3V the chip enters under voltage lock-out (UVLO) mode. UVLO consists of turning off both the top and bottom FETs and remaining in that condition until input voltage rises above 2.6V.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com VIN HG Q1 L1 SW/CSH LM3495 LG Q2 RILIM ILIM RSNS CSL Figure 35. Current Limit Sense Resistor When using a dedicated current limit sensing resistor, the equation governing the low-side current limit becomes: RILIM = ICL x RSNS 20 PA (6) MAXIMUM CURRENT SENSE In order to keep the low-side current sense amplifier within its linear range, the peak sense voltage, VSNS, between the CSL and SW/CSH pins should remain below 200 mV.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 PARALLEL LOW-SIDE SCHOTTKY DIODE Many synchronous buck regulators include a Schottky diode in parallel with the low-side power FET. The low forward drop and short reverse recovery time of Schottky diodes can improve efficiency by preventing the FET's body diode from turning on. This technique is most effective in circuits with output currents of 5A or less.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com MOSFETS Selection of the power FETs is governed by the same tradeoffs as switching frequency. Breaking down the losses in the high-side and low-side FETs is one way to determine relative efficiencies between different FETs. When using discrete SO-8 FETs the LM3495 is most efficient for output currents of 2A to 10A. Losses in the power FETs can be broken down into conduction loss, gate charging loss, and switching loss.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in micro henries. The second minimum inductance equation specific to the LM3495 is: 64 x (RDSON-LO + RSNS) LMIN2 = x fSW VIN VIN + 2 (17) By calculating in terms of milliohms and kilohertz the inductance value will come out in micro henries. For this design: LMIN1 = 13.2V - 1.2V x 0.1 = 0.8 PH 500 kHz x 3A LMIN2 = 64 x 3.4 m: 12V x = 0.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com VLIN5 DECOUPLING CAPACITOR The VLIN5 pin should always be decoupled with a 2.2 µF, 10V-rated ceramic capacitor placed as close as possible to the VLIN5 and PGND pins of the LM3495. The decoupling capacitor should have a minimum X5R or X7R type dielectric to ensure that the capacitance remains stable over the expected voltage and temperature range.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 RL L VO + C O VIN RO + RC RFB2 + - VRAMP GM VC + C1 C2 R1 + - 0.6V RFB1 Figure 36. Power Stage and Error Amp One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to determine.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com And the higher frequency pole is: ZL = fSW mC ± 0.5 (29) In the equation for APS, the output resistance, RO, is the output voltage divided by output current. DC gain is highest when output current is lowest. In order to design for the worst case, RO should be calculated for the minimum load current. For this example, no minimum load has been specified, so a load of 100 mA will be used (RO = 12Ω).
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 The value, B, can be determined by evaluating the power stage transfer function at the desired cross-over frequency, or by reading the value graphically from the power stage gain plot. Setting B equal to the inverse of the linear gain will force the total loop gain to be 1 (0dB) at the cross-over frequency. For this example the desired cross-over frequency is 1/10 of the switching frequency, or 50 kHz.
LM3495 www.ti.com 60 -60 40 -80 OVERALL LOOP PHASE (°) OVERALL LOOP GAIN (dB) SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 20 0 -20 -40 -60 100 1k 10k 100k 1M -100 -120 -140 -160 -180 100 FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) Figure 39. Overall Loop Gain and Phase The bandwidth of this example circuit is 49 kHz, with a phase margin of 46°.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Input Capacitor Loss This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this equation ‘n’ is the number of capacitors in parallel. PIN = I2rms-IN x ESR n Irms-IN = IO x D(1 - D) Irms-IN = 10 x 0.1(0.9) = 3A (48) (49) PIN = (3A)2 x 2mΩ) = 0.018W Output Inductor Loss PLOUT =(IO)2 x RL PLOUT = (10A)2 x 3 mΩ = 0.3W (50) (51) Total Loss PLOSS = 1.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com Table 1. Bill of Materials for 6.0V to 18.0V Input, 1.0V Output, 7A, 500 kHz ID Part Number Type Size U1 LM3495 Synchronous Controller TSSOP-16 Q1 Si4894DY N-MOSFET SO-8 Q2 Si4442DY N-MOSFET SO-8 D1 MBR0530 Schottky Diode Parameters Qty Vendor 1 TI 30V, 15mΩ, 11.5nC 1 Vishay 30V, 4.1mΩ, 36nC 1 Vishay SMA 30V, 0.5A 1 Vishay 12.5x12.8 x 4.7mm 2.7µH 8.7A 4.
LM3495 www.ti.com SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 Table 3. Bill of Materials for Typical Application Circuit ID Part Number Type Size U1 LM3495 Synchronous Controller TSSOP-16 Q1 HAT2198R N-MOSFET SO-8 Q2 HAT2165H N-MOSFET LFPAK D1 MBR0530 Schottky Diode L1 RLF12560T-1R0N140 Parameters Qty Vendor 1 TI 30V, 9.6mΩ, 11nC 1 Renesas 30V, 3.4mΩ, 33nC 1 Renesas SMA 30V, 0.5A 1 Vishay Inductor 12.5x12.
LM3495 SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision E (April 2013) to Revision F • 30 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3495MTCX TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM3495MTCX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3495MTCX TSSOP PW 16 2500 367.0 367.0 35.0 LM3495MTCX/NOPB TSSOP PW 16 2500 367.0 367.0 35.
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