Datasheet
FB
SNS
FPWM
PGND
CSL
LG
ILIM
SW/CSH
HG
BOOST
+
C
F
R
FB2
R
FB1
R
LIM
C
IN1
L1
Q1
Q2
C
B
D
1
1 PF
0.1 PF
Vin
Vo
LM3495
SGND
FREQ/SYNC
COMP/SD
VIN VLIN5
TRACK
C
DD
2.2PF
C
C1
R
C1
R
FRQ
C
C2
TRACK
IN
R
T1
R
T2
J3
C
SYNC
+ +
C
O1
C
O2
+
C
IN2
C
INX
C
OX
J1
VLIN5
ON/OFF
SKIP/FPWM
SYNC
IN
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15
16
J2
D
SYNC
L
IN
R
LG
D2
R
BST
C
SNB
R
SNB
TI Confidential - NDA Restrictions
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Additional Footprints
9 Additional Footprints
A 100 pF ceramic capacitor should be placed at position Dsync whenever the LM3495 runs without an
external clock. When an external clock is used, Dsync should be removed and a 100 pF ceramic
capacitor placed at Csync.
The 0Ω resistor J1 connects the TRACK pin and VDD pins of the LM3495 together. It should be removed
only when the tracking function is used.
The 0Ω resistor J2 connects the VIN and VLIN5 terminals of the LM3495 together. This resistor should be
used only when the input voltage is 5.5V or less, to provide maximum MOSFET gate drive.
The 0Ω resistor J3 connects the ‘Vin’ terminal to the VIN pin of the LM3495. This resistor should be
removed only for testing of the input current draw of the LM3495 IC.
The 0Ω resistor Rbst can be replaced with a higher value resistor to limit the current drawn by the BOOST
pin. This slows the high-side FET gate drive rise time and may reduce ringing on the switch node. Care
must be taken, as slowing the gate drive too much can cause shoot-through current.
Components Rt1 and Rt2 are used if the output of the converter is tracking another supply during startup.
For this application the output of the external supply should be connected to the TRACK IN terminal.
When the tracking feature is not used, the track pin should be connected to the VDD pin by placing a 0Ω
resistor in position J2.
Components Rsnb and Csnb can be used to filter ringing on the switch node.
D2 provides a position for a diode to go in parallel with Q2. In circuits with output currents of
approximately 5A or less, a Schottky diode at D2 can improve the efficiency of the converter.
10 Complete Circuit Schematic
Figure 3. Circuit Schematic
3
SNVA149B–March 2006–Revised April 2013 AN-1446 LM3495 Evaluation Board
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