Datasheet

1
2
3
4
5
10
9
8
7
6
VIN
VCC
RT
FB
UVO
SW
BST
N/C
RTN
UV
LM34923
SNVS695A –MARCH 2011–REVISED FEBRUARY 2013 www.ti.com
Connection Diagram
Figure 1. Top View
10-Lead VSSOP
Table 1. Pin Descriptions
Pin Name Description Application Information
No.
1 SW Switching Node Power switching node. Connect to the output inductor, re-circulating diode or synchronous
FET, and bootstrap capacitor.
2 BST Boost Pin An external capacitor is required between the BST and the SW pins (0.01uF or greater
ceramic). The BST pin capacitor is charged from VCC through an internal diode when SW is
low.
3 N/C Do not connect
4 RTN Ground pin Ground for the entire circuit.
5 UV Input pin for the under A resistor divider from VIN, or some other system voltage, programs the under-voltage
voltage indicator detection threshold. An internal current sink is enabled when UV is below 2.5V to provide
hysteresis.
6 UVO Under voltage status This open drain output is high when the UV pin voltage is below 2.5V, or when the VCC
UVLO
indicator function or the shutdown function is invoked.
7 FB Feedback Input from This pin is connected to the inverting input of the internal regulation comparator. The
Regulated Output regulation level is 2.5V.
8 RT/SD On-time set pin and A resistor between this pin and Vin sets the switch on-time as a function of Vin, and the
shutdown input frequency. The minimum recommended on-time is 200 ns at max input voltage. Taking this
pin to ground shuts off the regulator.
9 VCC Output from the internal The internal regulator provides bias supply for the Buck switch gate driver and other internal
high voltage series pass circuitry. A 1uF ceramic capacitor to ground is required. The regulator is current limited to
regulator. Regulated at ≈30 mA.
7.5V.
10 VIN Input Voltage The operating input range is 6V to 75V
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