Datasheet
3 x t
ON (max)
(R5//R6)
!
C8
V
OUT
FB
SW
RTN
BST
L1
R5
C4
LM34923
GND
VCC
3.01k:
82 PH
5V
C3
1 PF
R7
0.56:
C2
15 PF
0.01 PF
R6
3.01 k:
C8
0.01 PF
D1
V
OUT
FB
SW
RTN
BST
L1
C4
LM34923
GND
VCC
R5
3.01 k:
82 PH
5V
C3
1 PF
R7
1:
C2
15 PF
0.01 PF
R6
3.01 k:
D1
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Output Ripple Control
Figure 2. Lowest Cost Configuration
5.2 Option B) Reduced Ripple Configuration
This configuration generates less ripple at V
OUT
than Section 5.1 by the addition of one capacitor (C8)
across R5, as shown in Figure 3.
Figure 3. Reduced Ripple Configuration
Since the output ripple is passed by C8 to the FB pin with little or no attenuation, R7 can be reduced so
the minimum ripple at V
OUT
is ≊25 mVp-p. The minimum value for Cff is calculated from:
(2)
where t
ON(max)
is the maximum on-time (at minimum V
IN
), and R5//R6 is the parallel equivalent of the
feedback resistors. The ripple at V
OUT
ranges from 28 mVp-p to 159 mVp-p over the input voltage range,
see Figure 8.
3
SNVA482A–May 2011–Revised April 2013 AN-2147 LM34923 Evaluation Board
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