Datasheet
FB
SW
L1
C2
R1
R2
R3
LM34910C
BST
V
CC
D2
C3
C4
D1
I
SEN
S
GND
V
OUT1
V
OUT2
FB
SW
L1
C2
R1
R2
V
OUT2
R3
LM34910C
LM34910C
www.ti.com
SNVS517B –MAY 2007–REVISED MARCH 2013
Output voltage regulation is based on ripple voltage at the feedback input, requiring a minimum amount of ESR
for the output capacitor C2. The LM34910C requires a minimum of 25 mV of ripple voltage at the FB pin. In
cases where the capacitor’s ESR is insufficient additional series resistance may be required (R3 in Typical
Application Circuit and Block Diagram).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor as shown in Figure 3. However, R3 slightly degrades the load regulation.
Figure 3. Low Ripple Output Configuration
Start-up Regulator, V
CC
The start-up regulator is integral to the LM34910C. The input pin (V
IN
) can be connected directly to line voltage
up to 50V, with transient capability to 55V. The V
CC
output regulates at 7.0V, and is current limited to 9 mA. Upon
power up, the regulator sources current into the external capacitor at V
CC
(C3). When the voltage on the V
CC
pin
reaches the under-voltage lockout threshold of 5.8V, the buck switch is enabled and the Softstart pin is released
to allow the Softstart capacitor (C6) to charge up.
The minimum input voltage is determined by the regulator’s dropout voltage, the V
CC
UVLO falling threshold
(≊5.7V), and the frequency. When V
CC
falls below the falling threshold the V
CC
UVLO activates to shut off the
output. If V
CC
is externally loaded, the minimum input voltage increases since the output impedance at V
CC
is
≊140Ω. See Figure 1.
To reduce power dissipation in the start-up regulator, an auxiliary voltage can be diode connected to the V
CC
pin.
Setting the auxiliary voltage to between 8V and 14V shuts off the internal regulator, reducing internal power
dissipation. The sum of the auxiliary voltage and the input voltage (V
CC
+ V
IN
) cannot exceed 70V. Internally, a
diode connects V
CC
to V
IN
. See Figure 4.
Figure 4. Self Biased Configuration
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