Datasheet

LM3489
LM3489-Q1
SNVS443B –MAY 2006–REVISED FEBRUARY 2013 www.ti.com
Electrical Characteristics
(1)(2)
Specifications in Standard type face are for T
J
= 25°C, and in bold type face apply over the full Operating Temperature
Range (T
J
= −40°C to +125°C). Unless otherwise specified, V
IN
= 12V, V
ISNS
= V
IN
− 1V, and V
ADJ
= V
IN
− 1.1V. Datasheet
min/max specification limits are specified by design, test, or statistical analysis.
Symbol Parameter Test Conditions Min Typ Max Unit
I
SHDN
Shutdown input supply current EN = 0V 7 15 µA
V
EN
Enable threshold voltage Enable rising 1.15 1.5 1.85 V
V
EN_HYST
Enable threshold hysteresis 130 mV
I
Q
Quiescent Current at ground pin FB = 1.5V (Not Switching) 280 400 µA
V
FB
Feedback Voltage 1.223 1.239 1.255 V
(3)
1.214 1.264
V
HYST
Comparator Hysteresis 10 15 mV
14 20
V
CL_OFFSET
Current limit comparator offset V
FB
= 1.0V -20 0 +20 mV
I
CL_ADJ
Current limit ADJ current source V
FB
= 1.5V 3.0 5.5 7.0 µA
T
CL
Current limit one shot off time V
ADJ
= 11.5V 6 9 14 µs
V
ISNS
= 11.0V
V
FB
= 1.0V
R
PGATE
Driver resistance Source 5.5 Ω
I
SOURCE
= 100mA
Sink 8.5
I
SINK
= 100mA
I
PGATE
Driver Output current Source 0.44 A
V
IN
= 7V, PGATE = 3.5V
Sink 0.1
VIN = 7V, PGATE = 3.5V
I
FB
(4)
FB pin Bias Current V
FB
= 1.0V 300 750 nA
T
ONMIN_NOR
Minimum on time in normal V
ISNS
= V
ADJ
+ 0.1V 100 ns
operation C
load
on OUT = 1000pF
(5)
T
ONMIN_CL
Minimum on time in current limit V
ISNS
= V
ADJ
- 0.1V 200 ns
V
FB
= 1.0V
C
load
on OUT = 1000pF
(5)
%V
FB
/ΔV
IN
Feedback Voltage Line Regulation 4.5 ≤ V
IN
≤ 35V 0.01 %/V
(1) All limits are specified at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature
limits are 100% tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) The V
FB
is the trip voltage at the FB pin when PGATE switches from high to low.
(4) Bias current flows out from the FB pin.
(5) A 1000pF capacitor is connected between V
IN
and PGATE.
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