Datasheet

LM3485
SNVS178G –JANUARY 2002–REVISED FEBRUARY 2013 www.ti.com
Figure 8. Top Layer, Figure 9. Bottom Layer,
Typical PCB Layout (3.3V Output) Typical PCB Layout (3.3V Output)
Figure 10. Silk Screen,
Typical PCB Layout (3.3V Output)
C1: C
IN
22µF/35V EEJL1VD226R (Panasonic)
C2: C
OUT
100µF/6.3V 6TPC100M (Sanyo)
C3: C
ADJ
1nF Ceramic Chip Capacitor
C4: C
FF
100pF Ceramic Chip Capacitor
D1: 1A/40V MBRS140T3 (On Semiconductor)
L1: 22µH :QH66SN220M01L (Murata)
Q1: FDC5614P (Fairchild)
R1: 33kΩ Chip Resistor
R2: 20kΩ Chip Resistor
R3: R
ADJ
24kΩ Chip Resistor
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