Datasheet

LM3485
SNVS178G –JANUARY 2002–REVISED FEBRUARY 2013 www.ti.com
PROGRAMMING THE CURRENT LIMIT (R
ADJ
)
The current limit is determined by connecting a resistor (R
ADJ
) between input voltage and the ADJ pin.
R
ADJ
= I
IND_PEAK
* R
DSON
/I
CL_ADJ
(13)
where:
R
DSON
: Drain-Source ON resistance of the external PFET
I
CL_ADJ
: 3.0µA minimum
I
IND_PEAK
= I
LOAD
+ I
RIPPLE
/2
Using the minimum value for I
CL_ADJ
(3.0µA) ensures that the current limit threshold will be set higher than the
peak inductor current.
The R
ADJ
value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5V. With this in
mind, R
ADJ_MAX
= (V
IN
-3.5)/7µA. If a larger R
ADJ
value is needed to set the desired current limit, either use a
PFET with a lower R
DSON
, or use a current sense resistor as shown in Figure 6.
The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN.
CATCH DIODE SELECTION (D1)
The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average
power dissipation. The average current through the diode can be calculated as following.
I
D_AVE
= I
OUT
*
(1 − D) (14)
The off state voltage across the catch diode is approximately equal to the input voltage. The peak reverse
voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low
output voltage applications a low forward voltage provides improved efficiency. For high temperature
applications, diode leakage current may become significant and require a higher reverse voltage rating to
achieve acceptable performance.
P-CHANNEL MOSFET SELECTION (Q1)
The important parameters for the PFET are the maximum Drain-Source voltage (V
DS
), the on resistance (R
DSON
),
Current rating, and the input capacitance.
The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward
voltage. The V
DS
must be selected to provide some margin beyond the input voltage.
PFET drain current, Id, must be rated higher than the peak inductor current, I
IND-PEAK
.
Depending on operating conditions, the PGATE voltage may fall as low as V
IN
- 8.3V. Therefore, a PFET must
be selected with a V
GS
greater than the maximum PGATE swing voltage.
As input voltage decreases below 9V, PGATE swing voltage may also decrease. At 5.0V input the PGATE will
swing from V
IN
to V
IN
- 4.6V. To ensure that the PFET turns on quickly and completely, a low threshold PFET
should be used when the input voltage is less than 7V.
However, PFET switching losses will increase as the V
GS
threshold decreases. Therefore, whenever possible, a
high threshold PFET should be selected. Total power loss in the FET can be approximated using the following
equation:
PDswitch = R
DSON
*I
OUT
2
*D + F*I
OUT
*V
IN
*(t
on
+ t
off
)/2 (15)
where:
t
on
= FET turn on time
t
off
= FET turn off time
A value of 10ns to 20ns is typical for ton and toff.
A PFET should be selected with a turn on rise time of less than 100ns. Slower rise times will degrade efficiency,
can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin.
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