Datasheet

f
S
(V
SL
+ 50 x 10
-6
x R
SL
)
V
IN
1.8R
SN
+ D-0.5)
1
SQ
MAX
(
V
IN
1.8R
SN
+ D-0.5)
1
(
SQ
MIN
d
d
L
f
S
(V
SL
+ 50 x 10
-6
x R
SL
)
m
c
=
S
e
S
n
1+ =
1+
f
S
L(V
SL
+ 50 x 10
-6
x R
SL
)
1.8R
SN
V
IN
D' - V
Q
-V
SEN
1+
1.8R
SN
V
IN
D'
|
f
S
L(V
SL
+ 50 x 10
-6
x R
SL
)
D =
V
OUT
+ V
D
V
IN
+ V
D
- V
Q
-V
SEN
|
V
OUT
V
IN
Q =
1
Sm
c
x D' - 0.5)
V
OUT
(1-D)
L x f
S
(A)
'i
L(Pk-Pk)
=
LM3477
SNVS141K –OCTOBER 2000–REVISED MARCH 2013 www.ti.com
POWER INDUCTOR SECTION
The LM3477/A operates at a high switching frequency of 500kHz, which allows the use of small inductors. This is
made apparent in the following set of equations used to calculate the output voltage ripple.
ΔV
OUT(Pk-Pk)
≊ Δi
L(Pk-Pk)
x R
ESR
(V) (17)
(18)
As the switching frequency fs increases, the inductance required for a given output voltage ripple decreases. The
equations above for ΔV
OUT
and Δi
L
provide criteria for choosing the inductance. The maximum voltage ripple in
steady-state, PWM operation can be controlled by limiting Δi
L
which in turn is set by the inductance value.
Alternatively, one can simply choose Δi
L
as a percentage of the maximum output current. Clearly, the size of the
output capacitor ESR, R
ESR
, will have an affect on which criteria is used to choose the inductance. When the
ESR is relatively low (less than 100mΩ), such as in ceramic, OSCON, and some low ESR tantalum capacitors, it
is convenient to choose the inductance based on setting Δi
L
to 30% of Iout(max). If the ESR is high, then it may
be necessary to restrict Δi
L
to a lower value so that the output voltage ripple is not too high. Generally speaking,
the former suggestion of setting Δi
L
to 30% of I
OUT(MAX)
is recommended.
The inductance also affects the stability of the converter. The slopes S
n
and S
f
in Figure 22 are functions of the
inductance, while the compensation ramp, S
e
, is fixed by default. Therefore if the inductance is too small, the
converter may experience sub-harmonic oscillations. The LM3477/A provides sufficient internal slope
compensation to allow for inductances chosen according to the Δi
L
= 0.3 x I
OUT
guideline in most cases. Still, one
should check to make sure the inductance is not too low before continuing the design process. If it is found that
the selected inductance is too low, a patented scheme to increase the compensation ramp, S
e
, is provided in the
LM3477/A (see DEFAULT/ADJUSTABLE SLOPE COMPENSATION). In the calculations that follow, if it is found
that the chosen inductance is too small, R
SL
can be used to increase Se so that the inductance can be used.
In a current mode control architecture, there is an inherent resonance at half the switching frequency (see
DEFAULT/ADJUSTABLE SLOPE COMPENSATION ). A convenient indicator of how much resonance exists is
the quality factor Q. If Q is too high, subharmonic oscillations could occur, if Q is too low, the current mode
architecture begins to act like a voltage mode architecture and the necessary compensation becomes more
complex. This is discussed in more detail in Compensation, but here it is important to calculate Q to be sure the
selected inductance will not cause problems to the stability of the converter. The calculations below call for an
inductance that results in Q between 0.15 and 2. See Compensation if the chosen inductance enforces Q to be
out of this range. By default, no extra slope compensation is needed, so R
SL
= 0. In general, a Q between 0.5
and 1 is optimal.
(19)
Where,
D' = 1−D (20)
(21)
(22)
V
Q
= V
DS
of the MOSFET when it is conducting I
OUT
*R
DS(ON).
1.8 = voltage gain of the current sense amp.
V
SEN
= Voltage across the sense resistor ≊ I
OUT
x R
SN
Back solving for L gives a range for acceptable inductances based on a range for Q:
(23)
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