Datasheet

V
OUT
= 2.5V/2A
C
IN
C
OUT
R
FB1
R
FB2
L1
D1
Q1
10 PF
100 PF
10 PH
1k
2.15k
Si2343
LM3475
V
IN
EN
GND
PGATE
FB
1
2
3
4
5
C
FF
1 nF
V
IN
= 5V
5
PGATE
R
PGATE
3.3:
D1
C
SNUB
R
SNUB
L1
Q1
LM3475
www.ti.com SNVS239B –OCTOBER 2004–REVISED MARCH 2013
MOSFETs are very fast switching devices. The fast increase in PFET current coupled with parasitic trace
inductance can create unwanted noise spikes at both the switch node and at V
IN
. Switching noise will increase
with load current and input voltage. This noise can also propagate through the ground plane, sometimes causing
unpredictable device performance. Slowing the rise and fall times of the PFET can be very effective in reducing
this noise. Referring to Figure 15, the PFET can be slowed down by placing a small (1Ω-10Ω) resistor in series
with PGATE. However, this resistor will increase the switching losses in the PFET and will lower efficiency.
Therefore it should be kept as small as possible and only used when necessary. Another method to reduce
switching noise (other than good PCB layout, see Layout) is to use a small RC filter or snubber. The snubber
should be placed in parallel with the catch diode, connected close to the drain of the PFET, as shown in
Figure 15. Again, the snubber should be kept as small as possible to limit its impact on system efficiency. A
typical range is a 10Ω-100Ω resistor and a 470pF to 2.2nF ceramic capacitor.
Figure 15. PGATE Resistor and Snubber
Layout
PC board layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess
switching noise and poor operation.
As shown in Figure 17 and Figure 18, place the ground of the input capacitor as close as possible to the anode
of the diode. This path also carries a large AC current. The switch node, the node connecting the diode cathode,
inductor, and PFET drain, should be kept as small as possible. This node is one of the main sources for radiated
EMI.
The feedback pin is a high impedance node and is therefore sensitive to noise. Be sure to keep all feedback
traces away from the inductor and the switch node, which are sources of noise. Also, the resistor divider should
be placed close to the FB pin. The gate pin of the external PFET should be located close to the PGATE pin.
Using a large, continuous ground plane is also recommended, particularly in higher current applications.
Figure 16.
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