Datasheet

LM3463

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SNVS807A –MAY 2012–REVISED MAY 2013

Serial Interface Mode

Leaving MODE pin floating enables serial interface mode. In serial interface mode, the DIM01, DIM23 and DIM4

pins are used together as a serial data interface to accept external dimming control data frames serially. The

following table presents the functions of the DIM01, DIM23 and DIM4 pins in serial interface mode:

DIM01 Serial data packet input (8-bit packet size)

DIM23 Clock signal input for data bit latching

DIM4 End Of Frame (EOF) signal input for data packet loading

The DIM5 pin is not used in this mode and should connect to GND. Every data frame contains four 8–bit wide

data byte for PWM dimming control. Every data byte controls the PWM dimming duty of its corresponding output

channel(s): A hexadecimal 000h gives 0% dimming duty; a hexadecimal 0FFh gives 100% dimming duty.

Respectively, the first byte being loaded into the LM3463 controls the dimming duty of CH0 and CH1, the second

byte controls the dimming duty of CH2 and CH3, the third byte controls the dimming duty of CH4 and the forth

byte controls the dimming duty of CH5.

In serial interface mode, the six output channels are separated into four individual groups as listed in the

following table:

Group A CH0 and CH1, controlled by the first byte

Group B CH2 and CH3, controlled by the second byte

Group C CH4, controlled by the third byte

Group D controlled by the forth byte

A data bit is latched into the LM3463 by applying a rising edge to the DIM02 pin. After clocking 32 bits (4 data

bytes) into the LM3463, a falling edge should be applied to the DIM4 pin to indicate an EOF and load data bytes

from data buffer to output channels accordingly. Figure 31 shows the serial input waveforms to the LM3463 to

facilitate in serial interface mode. Figure 32 shows the timing parameters of the serial data interface. The PWM

dimming duty in the serial interface mode is governed by the following equation:

(12)

The PWM dimming duty at decimal data codes 01 (001h) and 02 (002h) are rounded up to 2/256. Thus the

minimum dimming duty in the serial interface mode is 2/256 or 0.781%. Figure 33 shows the relationship of the

PWM dimming duty and the code value of a data byte in the serial interface mode. The PWM dimming frequency

in serial interface mode is defined by the system clock of the LM3463. The dimming frequency in the serial

interface mode is equal to the system clock frequency divided by 256 which follows the equation below:

(13)

In order to achieve a 256 level (8–bit resolution) brightness control, the minimum on time of every channel

(1/(f

SERIAL-DIM

*256)) should be no shorter than 8us, thus a dimming frequency of 488Hz is suggested to use.

Product Folder Links: LM3463