Datasheet
V
IOUTADJ
Time
V
SEn
Time
Time
V
RAIL
0V
0V
V
RAIL
maintains as the
V
IOUADJ
equals 0.63V
V
RAIL(steady)
2.5V
V
SEn
changes
following V
IOUTADJ
0.63V
DHC resumes as
V
IOUTADJ
increases
to above 0.63V
Due to the changing of LED
current, DHC adjusts the
V
RAIL
to maintain constant
voltage headroom
LED current changes
with constant V
RAIL
V
RAIL
remains
constant when the
V
IOUTADJ
is equal
to or below 0.63V
LM3463
SNVS807A –MAY 2012–REVISED MAY 2013
www.ti.com
Figure 23. Holding V
RAIL
when V
IOUTADJ
is below 0.63V
System Startup
When the LM3463 is powered, the internal Operational Transconductance Amplifier (OTA) charges the capacitor
C
DHC
through the CDHC pin. As the voltage at the CDHC pin increases, the voltage at the OutP pin starts to
reduce from V
CC
. When the voltage of the OutP pin falls below V
FB
+ 0.7V, the OutP pin sinks current from the
V
FB
node and eventually pulls up the output voltage of the primary power supply (V
RAIL
). As the V
RAIL
reaches
V
DHC_READY
, the LM3463 performs a test to identify the status of the LED strings (short / open circuit of LED
strings). The V
DHC_REDAY
is defined by an external voltage divider which consists of R
FB1
and R
FB2
. The
V
DHC_READY
is calculated following the equation:
(7)
After the test is completed, the LM3463 turns on the LED strings with regulated output currents. At the moment
that the LM3463 turns the LEDs on, the OutP pin stops sinking current from the V
FB
node and in turn V
RAIL
slews
down. Along with the decreasing of V
RAIL
, the voltage at the V
DRn
pins falls to approach 1V. When a V
DRn
is
decreased to 1V, the DHC loop enters a steady state to maintain the lowest V
DRn
to 1V average at a slow
manner defined by C
DHC
. Figure 24 presents the changes of V
RAIL
from system power up to DHC loop enters
steady state.
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