Datasheet

LM3463
www.ti.com SNVS807A –MAY 2012–REVISED MAY 2013
System Clock Generator
The LM3463 includes an internal clock generator which is used to provide clock signal to the internal digital
circuits. The clock frequency at the CLKOUT pin is equal to 1/2 of the frequency of the internal system clock
generator. The system clock generator governs the rate of operation of the following functions:
• PWM dimming frequency in Serial Interface Mode
• PWM dimming frequency in DC Interface Mode
• Clock frequency in cascade operation (CLKOUT pin)
The system clock frequency is defined by the value of an external resistor, R
FS
following the equation:
(5)
Operation Mode CLKOUT Freq. Dimming Freq. R
FS
Serial Interface Mode 125 kHz 488. 3Hz 125 kΩ
DC Interface Mode 625 kHz 488.3Hz 62.2 kΩ
Direct PWM Mode 625 kHz Virtually no limit 62.2 kΩ
Dynamic Headroom Control (DHC)
The Dynamic Headroom Control (DHC) is a control method which aimed at minimizing the voltage drops on the
linear regulators to optimize system efficiency. The DHC circuit inside the LM3463 controls the output voltage of
the primary power supply (V
RAIL
) until the voltage at any drain voltage sensing pin (V
DRn
) equals 1V. The LM3463
interacts with the primary power supply through the OutP pin in a slow manner which determined by the
capacitor, C
DHC
. Generally, the value of the C
DHC
defines the frequency response of the LM3463. The higher the
capacitance of the C
DHC
, the lower the frequency response of the DHC loop, and vice versa. Since the V
RAIL
is
controlled by the LM3463 via the DHC loop, the response of the LM3463 driver stage must be set one decade
lower than the generic response of the primary power supply to secure stable operation.
The cut-off frequency of the DHC loop is governed by the following equation:
(6)
Practically, the frequency response of the primary power supply might not be easily identified (e.g. off-the-shelf
AC/DC power supply). For the situations that the primary power supply has an unknown frequency response, it is
suggested to use a 2.2uF 10V X7R capacitor for CDHC as an initial value and decrease the value of the C
DHC
to
increase the response of the whole system as needed.
Holding V
RAIL
In Analog Dimming Control
Due to the V-I characteristic of the LED, the forward voltage of the LED strings decreases when the forward
current is decreased. In order to compensate the rising of the voltage drop on the linear regulators when
performing analog dimming control (due to the reduction of LED forward voltages), the DHC circuit in the LM3463
reduces the rail voltage (V
RAIL
) to maintain minimum voltage headroom (i.e. minimum V
DRn
).
In order to ensure good response of analog dimming control, the V
RAIL
is maintained at a constant level to
provide sufficient voltage headroom when the output currents are adjusted to a very low level. When the voltage
at the IOUTADJ pin is decreased from certain level to below 0.63V, the DHC circuit stops to react to the
changing of V
DRn
and maintains the V
RAIL
at the level while V
IOUTADJ
equals 0.63V. DHC resumes when the
V
IOUTADJ
is increased to above 0.63V. Figure 23 shows the relationship of the V
RAIL
, V
SEn
and V
IOUTADJ
.
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