Datasheet

GND
+
-
5 P$
40 k:
Rectified AC
BIAS
AC
AC
LM3450/50A
Sample
C
HLD
C
SEN
R
SEN
R
HLD
Q
PS
R
BS
+
-
V
SEN
I
SEN
HOLD
10k
NTC
15k
3904
Connect if thermal
protection circuit is
not desired
Q
PS
thermal
protection
circuit
0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
DIM PIN DUTY CYCLE (INVERTED)
LM3450/A DEMODULATED VAC PIN DUTY CYCLE
1V
0.5V
2V
2.5V
1.5V
V
ADJ
=3V
LM3450
www.ti.com SNVS681D –NOVEMBER 2010–REVISED MAY 2013
Figure 30. Complete Decoder Mapping
Since the buffered decoder output has amplitude equal to V
ADJ
and the resulting PWM signal is filtered into an
analog voltage at FLT2, the V
ADJ
pin can be used to change the mapping as shown in Figure 30. The maximum
LED current (DIM = 0) when V
ADJ
= 3V corresponds to decoded angles of 70% or greater. Some dimmers have a
maximum angle greater than this. If V
ADJ
is reduced to 2.5V, the maximum LED current will correspond to an
angle of 80% and at V
ADJ
= 2V the maximum will occur at a decoded angle of 95%.
The V
ADJ
pin can also be used to implement a standard analog adjust function. If the demodulated phase angle
at V
AC
is above 85%, then the fast filter is always enabled (500kΩ shorted) and the V
ADJ
pin can solely be used
to scale the DIM pin duty cycle. When V
ADJ
is pulled below 75mV the part enters low power shutdown so the
maximum attainable contrast ratio using V
ADJ
only is approximately 40:1.
Both FLT1 and FLT2 have pull-down MosFETs that are turned on when V
CC
UVLO falling threshold is triggered.
This provides a quick discharge path for the capacitors and eliminates the possibility of an undesired light level at
the next startup.
Figure 31. Dynamic Hold Circuit
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