Datasheet

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LM3450
www.ti.com SNVS681D –NOVEMBER 2010–REVISED MAY 2013
LOW POWER SHUTDOWN
The LM3450/50A can be placed into a low power shutdown by grounding the V
ADJ
pin (any voltage below 75mV).
During low power shutdown, the device will turn on the GATE for one cycle followed by a fixed off-time of 42µs
and the cycle repeats. During shutdown, the DIM output will be high (zero light output) since the buffer rail at
FLT1 will be at or near zero. This feature is designed to hold up the PFC output voltage while removing the load
(turning the LEDs off).
THERMAL SHUTDOWN
Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction
temperature is exceeded. The threshold for thermal shutdown is 160°C with a 20°C hysteresis. During thermal
shutdown GATE is disabled.
Figure 24. Phase Dimming Waveforms
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