Datasheet

1
4
3
2
16
13
14
15
ASNS
DIM
GND
FLTR1
COFF
FLTR2
5 12
BLDR
ISNS
11
NC
NC
VCC
GND
10
8 9
SW
SW
6
7
SW
SW
LM3448
SNOSB51C –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com
Connection Diagram
Top View
Figure 2. 16-Lead Narrow SOIC Package
PIN DESCRIPTIONS
Pin(s) Name Description
1, 2, 15, SW Drain connection of internal 600V MOSFET.
16
3, 14 NC No connect. Provides clearance between high voltage and low voltage pins. Do not tie to GND.
4 BLDR Bleeder pin. Provides the input signal to the angle detect circuitry. A 230Ω internal resistor ensures BLDR is pulled
down for proper angle sense detection.
5, 12 GND Circuit ground connection.
6 VCC Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. Connect a 22uF
(minimum) bypass capacitor to ground.
7 ASNS PWM output of the TRIAC dim decoder circuit. Outputs a 0 to 4V PWM signal with a duty cycle proportional to the
TRIAC dimmer on-time.
8 FLTR1 First filter input. The 120Hz PWM signal from ASNS is filtered to a DC signal and compared to a 1 to 3V, 5.85 kHz
ramp to generate a higher frequency PWM signal with a duty cycle proportional to the TRIAC dimmer firing angle.
Pull above 4.9V (typical) to TRI-STAT DIM.
9 DIM Input/output dual function dim pin. This pin can be driven with an external PWM signal to dim the LEDs. It may
also be used as an output signal and connected to the DIM pin of other LM3448/LM3445 devices or LED drivers
to dim multiple LED circuits simultaneously.
10 COFF OFF time setting pin. A user set current and capacitor connected from the output to this pin sets the constant OFF
time of the switching controller.
11 FLTR2 Second filter input. A capacitor tied to this pin filters the PWM dimming signal to supply a DC voltage to control the
LED current. Could also be used as an analog dimming input.
13 ISNS LED current sense pin (internally connected to MOSFET source). Connect a resistor from ISNS to GND to set the
maximum LED current.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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