Datasheet

LM3448
SNOSB51C –SEPTEMBER 2011–REVISED MAY 2013 www.ti.com
The Angle Detect circuit and its filter produce a DC level which corresponds to the duty cycle (relative on-time) of
the TRIAC dimmer. As a result, the LM3448 will work equally well with 50Hz or 60Hz line voltages.
BLEEDER
While the BLDR pin is below the 7.21V threshold, the internal bleeder MOSFET is on to place a small load
(230Ω) on the series pass regulator. This additional load is necessary to complete the circuit through the TRIAC
dimmer so that the dimmer delay circuit can operate correctly. Above 7.21V, the bleeder resistor is removed to
increase efficiency.
FLTR1 PIN
The FLTR1 pin has two functions. Normally it is fed by ASNS through filter components R1 and C3 and drives
the dim decoder. However if the FLTR1 pin is tied above 4.9V ( e.g., to VCC) the ramp comparator is at TRI-
STATE disabling the dim decoder.
DIM DECODER
The ramp generator produces a 5.85 kHz saw tooth wave with a minimum of 1.0V and a maximum of 3.0V. The
filtered ASNS signal enters pin FLTR1 where it is compared against the output of the Ramp Generator. The
output of the ramp comparator will have an on-time which is inversely proportional to the average voltage level at
pin FLTR1. However since the FLTR1 signal can vary between 0V and 4.0V (the limits of the ASNS pin), and the
ramp generator signal only varies between 1.0V and 3.0V, the output of the ramp comparator will be on
continuously for V
FLTR1
< 1.0V and off continuously for V
FLTR1
> 3.0V. This allows a decoding range from 45° to
135° to provide a 0 – 100% dimming range.
The output of the ramp comparator drives both a common source N-channel MOSFET through a Schmitt trigger
and the DIM pin. The MOSFET drain is pulled up to 750 mV by a 50kΩ resistor.
Since the MOSFET inverts the output of the ramp comparator, the drain voltage of the MOSFET is proportional
to the duty cycle of the line voltage that comes through the TRIAC dimmer. The amplitude of the ramp generator
causes this proportionality to "hard limit" for duty cycles above 75% and below 25%.
FLTR2
The MOSFET drain signal next passes through an RC filter comprised of an internal 370kΩ resistor and an
external capacitor on pin FLTR2. This forms a second low pass filter to further reduce the ripple in this signal
which is used as a reference by the PWM comparator. This RC filter is generally set to 10Hz.
The net effect is that the output of the dim decoder is a DC voltage whose amplitude varies from near 0V to 750
mV as the duty cycle of the dimmer varies from 25% to 75%. This corresponds to conduction angles of 45° to
135°.
The output voltage of the dim decoder directly controls the peak current that will be delivered by the internal SW
FET.
As the TRIAC fires beyond 135°, the DIM decoder no longer controls the dimming. At this point the LEDs will dim
gradually for one of two reasons:
• The voltage at V
BUCK
decreases and the buck converter runs out of headroom and causes LED current to
decrease as V
BUCK
decreases.
• Minimum on-time is reached which fixes the duty-cycle and therefore reduces the voltage at V
BUCK
.
The transition from dimming with the DIM decoder to headroom or minimum on-time dimming is seamless. LED
currents from full load to as low as 0.5mA can be easily achieved.
COFF AND CONSTANT OFF-TIME CONTROL OVERVIEW
The LM3448 is a buck regulator that uses a proprietary constant off-time method to maintain constant current
through a string of LEDs as shown in Figure 20.
12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM3448