Datasheet
T
ON
ADJ
EN
COMP
DIM
NC
SS
V
IN
NC
CGND
V
EE
HS
HO
V
CC
12
11
10
9
8
7
13
14
18
17
16
15
1
2
3
4
5
6
21
22
23
24
LS
LO
NC
BST
LM3433
19
20
BST2
CSN
NC
CSP
DIMR
DIMO
LM3433
SNVS535C –OCTOBER 2007–REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
Top View
Figure 1. 24-Lead QFN
See RTW Package
PIN DESCRIPTIONS
Pin Name Function
On-time programming pin. Tie an external resistor (R
ON
) from T
ON
to CSN, and a capacitor (C
ON
) from T
ON
to V
EE
.
1 T
ON
This sets the nominal operating frequency when the LED is fully illuminated.
Analog LED current adjust. Tie to V
IN
for fixed 60mV average current sense resistor voltage. Tie to an external
reference to adjust the average current sense resistor voltage (programmed output current). Refer to the "V
SENSE
vs.
2 ADJ
ADJ Voltage" graphs in the Typical Performance Characteristics section and the Design Procedure section of the
datasheet.
Enable pin. Connect this pin to logic level HI or V
IN
for normal operation. Connect this pin to CGND for low current
3 EN
shutdown. EN is internally tied to V
IN
through a 100k resistor.
4 DIM Logic level input for LED PWM dimming. DIM is internally tied to CGND through a 100k resistor.
5 V
IN
Logic power input: Connect to positive voltage between +3.0V and +5.8V w.r.t. CGND.
6 CGND Chassis ground connection.
7 V
EE
Negative voltage power input: Connect to voltage between –14V to –9V w.r.t. CGND.
8 COMP Compensation pin. Connect a capacitor between this pin and V
EE
.
9 NC No internal connection. Tie to V
EE
or leave open.
Soft Start pin. Tie a capacitor from SS to V
EE
to reduce input current ramp rate. Leave pin open if function is not
10 SS
used. The SS pin is pulled to V
EE
when the device is not enabled.
11 NC No internal connection. Tie to V
EE
or leave open.
12 NC No internal connection. Tie to V
EE
or leave open.
13 LS Low side FET gate drive return pin.
14 LO Low side FET gate drive output. Low in shutdown.
Low side FET gate drive power bypass connection and boost diode anode connection. Tie a 2.2µF capacitor
15 V
CC
between V
CC
and V
EE
.
16 BST High side "synchronous" FET drive bootstrap rail.
17 HO High side "synchronous" FET gate drive output. Pulled to HS in shutdown.
18 HS Switching node and high side "synchronous" FET gate drive return.
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